1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46240000 /* hex */ 14#define MHU_RX_ADDR 46250000 /* hex */ 15 16#define LIT_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" 17#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" 18#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3" 19 20#define RSE_MHU_TX_ADDR 49020000 /* hex */ 21#define RSE_MHU_RX_ADDR 49030000 /* hex */ 22 23#define ETHERNET_ADDR 64000000 24#define ETHERNET_INT 799 25 26#define SYS_REGS_ADDR 60080000 27 28#define MMC_ADDR 600b0000 29#define MMC_INT_0 778 30#define MMC_INT_1 779 31 32#define RTC_ADDR 600a0000 33#define RTC_INT 777 34 35#define KMI_0_ADDR 60100000 36#define KMI_0_INT 784 37#define KMI_1_ADDR 60110000 38#define KMI_1_INT 785 39 40#define VIRTIO_BLOCK_ADDR 60020000 41#define VIRTIO_BLOCK_INT 769 42 43#include "tc-common.dtsi" 44#if TARGET_FLAVOUR_FVP 45#include "tc-fvp.dtsi" 46#else 47#include "tc-fpga.dtsi" 48#endif /* TARGET_FLAVOUR_FVP */ 49#include "tc3-4-base.dtsi" 50 51/ { 52 smmu_700: iommu@3f000000 { 53 status = "okay"; 54 }; 55 56 smmu_700_dpu: iommu@4002a00000 { 57 status = "okay"; 58 }; 59 60 dp0: display@DPU_ADDR { 61 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 62 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 63 }; 64 65 gpu: gpu@2d000000 { 66 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>; 67 interrupt-names = "IRQAW"; 68 iommus = <&smmu_700 0x200>; 69 }; 70 71 dsu-pmu { 72 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; 73 }; 74}; 75