1 /* 2 * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <lib/el3_runtime/pubsub.h> 13 #include <lib/extensions/spe.h> 14 15 #include <plat/common/platform.h> 16 17 void spe_enable(cpu_context_t *ctx) 18 { 19 el3_state_t *state = get_el3state_ctx(ctx); 20 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 21 22 /* 23 * MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state 24 * and disabled in secure state. Accesses to SPE registers at 25 * S-EL1 generate trap exceptions to EL3. 26 * 27 * MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses. 28 * When FEAT_RME is not implemented, this field is RES0. 29 * 30 * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1 31 * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented. 32 * Setting this bit to 1 doesn't have any effect on it when 33 * FEAT_SPEv1p2 not implemented. 34 */ 35 mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT; 36 mdcr_el3_val &= ~(MDCR_NSPBE_BIT); 37 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 38 } 39 40 void spe_disable(cpu_context_t *ctx) 41 { 42 el3_state_t *state = get_el3state_ctx(ctx); 43 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 44 45 /* 46 * MDCR_EL3.NSPB: Clear these bits to disable SPE feature, as it was enabled 47 * for Non-secure state only. After clearing these bits Secure state owns 48 * the Profiling Buffer and accesses to Statistical Profiling and Profiling 49 * Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3 50 * 51 * MDCR_EL3.NSPBE: Don't care as it was cleared during spe_enable and setting 52 * this to 1 does not make sense as NSPBE{1} and NSPB{0b0x} is RESERVED. 53 * 54 * MDCR_EL3.EnPMSN (ARM v8.7): Clear the bit to trap access of PMSNEVFR_EL1 55 * from EL2/EL1 to EL3. 56 */ 57 mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT); 58 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 59 } 60 61 void spe_init_el2_unused(void) 62 { 63 uint64_t v; 64 65 /* 66 * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical 67 * profiling controls to EL2. 68 * 69 * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure 70 * state. Accesses to profiling buffer controls at 71 * Non-secure EL1 are not trapped to EL2. 72 */ 73 v = read_mdcr_el2(); 74 v &= ~MDCR_EL2_TPMS; 75 v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1); 76 write_mdcr_el2(v); 77 } 78