Changes necessary to support SEPARATE_NOBITS_REGION feature

Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes a

Changes necessary to support SEPARATE_NOBITS_REGION feature

Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes are needed to support it completely.

1. adr instruction only allows computing the effective address
of a location only within 1MB range of the PC. However, adrp
instruction together with an add permits position independent
address of any location with 4GB range of PC.

2. Since BL31 _RW_END_ marks the end of BL31 image, care must be
taken that it is aligned to page size since we map this memory
region in BL31 using xlat_v2 lib utils which mandate alignment of
image size to page granularity.

Change-Id: I3451cc030d03cb2032db3cc088f0c0e2c84bffda
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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T589: Fix insufficient ordering guarantees in bakery lock

bakery_lock_get() uses DMB LD after lock acquisition and
bakery_lock_release() uses DMB ST before releasing the lock. This is
insufficient i

T589: Fix insufficient ordering guarantees in bakery lock

bakery_lock_get() uses DMB LD after lock acquisition and
bakery_lock_release() uses DMB ST before releasing the lock. This is
insufficient in both cases. With just DMB LD, stores in the critical
section can be reordered before the DMB LD which could mean writes in
the critical section completing before the lock has been acquired
successfully. Similarly, with just DMB ST, a load in the critical section
could be reordered after the the DMB ST. DMB is the least expensive
barrier that can provide the required ordering.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
Change-Id: Ieb74cbf5b76b09e1789331b71f37f7c660221b0e

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Neovers N1: added support to update presence of External LLC

CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal L

Neovers N1: added support to update presence of External LLC

CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.

To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363

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Merge "xlat_tables_v2: simplify end address checks in mmap_add_region_check()" into integration

Merge "Prevent speculative execution past ERET" into integration

Merge "Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"" into integration

Errata workarounds N1 1043202, 1315703 default off

Setting errata workarounds for N1 1043202 and 1315703 to 0 since
they should be turned off by default.

Signed-off-by: Lauren Wehrmeister <lauren.w

Errata workarounds N1 1043202, 1315703 default off

Setting errata workarounds for N1 1043202 and 1315703 to 0 since
they should be turned off by default.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9

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qemu: Implement qemu_system_off via semihosting.

This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.

Sig

qemu: Implement qemu_system_off via semihosting.

This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03

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Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"

This reverts commit 76d84cbc60ab3ee7bf40d53487f85ed7417bdcc3.

Change-Id: I867af7af3d9f5e568101f79b9ebea578e5cb2a4b

Prevent speculative execution past ERET

Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump

Prevent speculative execution past ERET

Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).

This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8
https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61
https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2
https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a

It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c

Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f

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xlat_tables_v2: simplify end address checks in mmap_add_region_check()

Use end_va and end_pa defined at the beginning of this function.

Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c
Signed-o

xlat_tables_v2: simplify end address checks in mmap_add_region_check()

Use end_va and end_pa defined at the beginning of this function.

Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Changes necessary to support SEPARATE_NOBITS_REGION feature

Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes a

Changes necessary to support SEPARATE_NOBITS_REGION feature

Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes are needed to support it completely.

1. adr instruction only allows computing the effective address
of a location only within 1MB range of the PC. However, adrp
instruction together with an add permits position independent
address of any location with 4GB range of PC.

2. Since BL31 _RW_END_ marks the end of BL31 image, care must be
taken that it is aligned to page size since we map this memory
region in BL31 using xlat_v2 lib utils which mandate alignment of
image size to page granularity.

Change-Id: Ic745c5a130fe4239fa2742142d083b2bdc4e8b85
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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compiler_rt: Import popcountdi2.c and popcountsi2.c files

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

This is to get the __popcountsi2(si_

compiler_rt: Import popcountdi2.c and popcountsi2.c files

Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

This is to get the __popcountsi2(si_int a) and __popcountdi2(di_int a)
builtin which are required by a driver that uses a __builtin_popcount().

Change-Id: I8e0d97cebdd90d224690c8ce1b02e657acdddb25
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Merge changes from topic "ld/mtd_framework" into integration

* changes:
io: change seek offset to signed long long
compiler_rt: Import aeabi_ldivmode.S file and dependencies

Unify type of "cpu_idx" across PSCI module.

NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned i

Unify type of "cpu_idx" across PSCI module.

NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned int" type.

Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.

2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent

Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.

Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c

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compiler_rt: Import aeabi_ldivmode.S file and dependencies

Import aeabi_ldivmod.S with divmoddi4.c and divdi3.c from the
LLVM compiler_rt library on master branch as of 30 Oct 2018
(SVN revision: r3

compiler_rt: Import aeabi_ldivmode.S file and dependencies

Import aeabi_ldivmod.S with divmoddi4.c and divdi3.c from the
LLVM compiler_rt library on master branch as of 30 Oct 2018
(SVN revision: r345645).

This is to get the __aeabi_ldivmod builtin, which is required
by a patch using signed long long division.

Change-Id: Iee4c421deb3175142655e19074cd3732edd82227
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Workaround for Hercules erratum 1688305

Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined

Workaround for Hercules erratum 1688305

Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.

Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "debugfs: add SMC channel" into integration

Merge "debugfs: add FIP device" into integration

Merge "debugfs: add 9p device interface" into integration

spm: Remove SPM Alpha 1 prototype and support files

The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component

spm: Remove SPM Alpha 1 prototype and support files

The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.

This patch removes:

- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions

Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>

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debugfs: add SMC channel

Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.

Signed-

debugfs: add SMC channel

Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.

Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d

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aarch64: Fix stack pointer maintenance on EA handling path

EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
res

aarch64: Fix stack pointer maintenance on EA handling path

EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
resulted in el3_exit setting runtime stack to context. This in turn
caused memory corruption on consecutive EL3 entries.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0424245c27c369c864506f4baa719968890ce659

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debugfs: add FIP device

Add a FIP driver hooked to debugfs 9p interface. This is an
abstraction of the FIP filesystem layer on top of a mass storage,
or memory block driver.

Signed-off-by: Olivier

debugfs: add FIP device

Add a FIP driver hooked to debugfs 9p interface. This is an
abstraction of the FIP filesystem layer on top of a mass storage,
or memory block driver.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If275ea0824763de43ab666dab2a06de5352ff940

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debugfs: add 9p device interface

The 9p interface provides abstraction layers allowing the software
that uses devices to be independent from the hardware.

This patch provides a file system abstract

debugfs: add 9p device interface

The 9p interface provides abstraction layers allowing the software
that uses devices to be independent from the hardware.

This patch provides a file system abstraction to link drivers to their
devices and propose a common interface to expose driver operations to
higher layers. This file system can be used to access and configure a
device by doing read/write operations.

Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255

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