SPE: Fix feature detection

Currently the feature test for the SPE extension requires the feature
bits in the ID_AA64DFR0 register to read exactly 0b0001.
However the architecture guarantees that any

SPE: Fix feature detection

Currently the feature test for the SPE extension requires the feature
bits in the ID_AA64DFR0 register to read exactly 0b0001.
However the architecture guarantees that any values greater than 0
indicate the presence of a feature, which is what we are after in
our spe_supported() function.

Change the comparison to include all values greater than 0.

This fixes SPE support in non-secure world on implementations which
include the Scalable Vector Extension (SVE), for instance on Zeus cores.

Change-Id: If6cbd1b72d6abb8a303e2c0a7839d508f071cdbe
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "libc: Import strlcat from FreeBSD project" into integration

Merge "libc: Add support for vsnprintf()" into integration

libc: Add support for vsnprintf()

It uses the existing implementation of snprintf() function

Change-Id: Ie59418564c2e415222e819cf322c34e9a4d1f336
Signed-off-by: Madhukar Pappireddy <madhukar.pappir

libc: Add support for vsnprintf()

It uses the existing implementation of snprintf() function

Change-Id: Ie59418564c2e415222e819cf322c34e9a4d1f336
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "Workaround for Neoverse N1 erratum 1868343" into integration

Workaround for Neoverse N1 erratum 1868343

Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACT

Workaround for Neoverse N1 erratum 1868343

Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.

SDEN can be found here:
https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844

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libc: Import strlcat from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
Made small changes to fit into TF-A project

Change-Id: I07fd7fe1037857f6b299c35367c104fb51fa5cfa
Sign

libc: Import strlcat from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
Made small changes to fit into TF-A project

Change-Id: I07fd7fe1037857f6b299c35367c104fb51fa5cfa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "libc: memset: improve performance by avoiding single byte writes" into integration

libc: memset: improve performance by avoiding single byte writes

Currently our memset() implementation is safe, but slow. The main reason
for that seems to be the single byte writes that it issues,

libc: memset: improve performance by avoiding single byte writes

Currently our memset() implementation is safe, but slow. The main reason
for that seems to be the single byte writes that it issues, which can
show horrible performance, depending on the implementation of the
load/store subsystem.

Improve the algorithm by trying to issue 64-bit writes. As this only
works with aligned pointers, have a head and a tail section which
covers unaligned pointers, and leave the bulk of the work to the middle
section that does use 64-bit writes.

Put through some unit tests, which exercise all combinations of nasty
input parameters (pointers with various alignments, various odd and even
sizes, corner cases of content to write (-1, 256)).

Change-Id: I28ddd3d388cc4989030f1a70447581985368d5bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration

psci: utility api to invoke stop for other cores

The API can be used to invoke a 'stop_func' callback for all
other cores from any initiating core. Optionally it can also
wait for other cores to pow

psci: utility api to invoke stop for other cores

The API can be used to invoke a 'stop_func' callback for all
other cores from any initiating core. Optionally it can also
wait for other cores to power down. There may be various use
of such API by platform. Ex: Platform may use this to power
down all other cores from a crashed core.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: I4f9dc8a38d419f299c021535d5f1bcc6883106f9

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plat/arm: Introduce and use libc_asm.mk makefile

Trace analysis of FVP_Base_AEMv8A 0.0/6063 model
running in Aarch32 mode with the build options
listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM

plat/arm: Introduce and use libc_asm.mk makefile

Trace analysis of FVP_Base_AEMv8A 0.0/6063 model
running in Aarch32 mode with the build options
listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.99% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch introduces new libc_asm.mk makefile which
replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 20.56%.
The number of CPU instructions (Inst) executed during
TF-A boot stage before start of BL33 in RELEASE builds
for different versions is presented in the tables below,
where:
- C TF-A: existing TF-A C code;
- C musl: "lightweight code" C "implementation of the
standard library for Linux-based systems"
https://git.musl-libc.org/cgit/musl/tree/src/string/memset.c
- Asm Opt: assemler version from "Arm Optimized Routines"
project
https://github.com/ARM-software/optimized-routines/blob/
master/string/arm/memset.S
- Asm Linux: assembler version from Linux kernel
https://github.com/torvalds/linux/blob/master/arch/arm/lib/memset.S
- Asm TF-A: assembler version from this patch

Aarch32:
+-----------+------+------+--------------+----------+
| Variant | Set | Size | Inst | Ratio |
+-----------+------+------+--------------+----------+
| C TF-A | T32 | 16 | 2122110003 | 1.000000 |
| C musl | T32 | 156 | 1643917668 | 0.774662 |
| Asm Opt | T32 | 84 | 1604810003 | 0.756233 |
| Asm Linux | A32 | 168 | 1566255018 | 0.738065 |
| Asm TF-A | A32 | 160 | 1525865101 | 0.719032 |
+-----------+------+------+--------------+----------+

AArch64:
+-----------+------+------------+----------+
| Variant | Size | Inst | Ratio |
+-----------+------+------------+----------+
| C TF-A | 28 | 2732497518 | 1.000000 |
| C musl | 212 | 1802999999 | 0.659836 |
| Asm TF-A | 140 | 1680260003 | 0.614917 |
+-----------+------+------------+----------+

This patch modifies 'plat\arm\common\arm_common.mk'
by overriding libc.mk makefile with libc_asm.mk and
does not effect other platforms.

Change-Id: Ie89dd0b74ba1079420733a0d76b7366ad0157c2e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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lib: cpu: Check SCU presence in DSU before accessing DSU registers

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT"

lib: cpu: Check SCU presence in DSU before accessing DSU registers

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3
memory system variant is used, there won't be any L3 cache,
snoop filter, and SCU logic present hence no system control register
will be present. Hence check SCU presence before accessing DSU register
for DSU_936184 errata.

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63

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cpus: denver: skip DCO enable/disable for recent SKUs

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3a

cpus: denver: skip DCO enable/disable for recent SKUs

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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lib: cpus: denver: add MIDR PN9 variant

This patch introduces support for PN9 variant for some
Denver based platforms.

Original change by: Hemant Nigam <hnigam@nvidia.com>

Signed-off-by: Kalyani C

lib: cpus: denver: add MIDR PN9 variant

This patch introduces support for PN9 variant for some
Denver based platforms.

Original change by: Hemant Nigam <hnigam@nvidia.com>

Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3

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cpus: denver: introduce macro to declare cpu_ops

This patch introduces a macro to declare cpu_op for all Denver
SKUs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibcf88c3256fc5dca

cpus: denver: introduce macro to declare cpu_ops

This patch introduces a macro to declare cpu_op for all Denver
SKUs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977

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Add support for hexadecimal and pointer format specifiers to snprintf()

The current implementation of snprintf() does not support pointer and
hexadecimal format specifiers, which can be needed, for

Add support for hexadecimal and pointer format specifiers to snprintf()

The current implementation of snprintf() does not support pointer and
hexadecimal format specifiers, which can be needed, for instance, for
DTB manipulations.

This patch adds that functionality by borrowing some code from the
printf() implementation.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I2076ea46693a73a04890982bf20e3c633c2767fb

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lib: cpus: sanity check pointers before use

The cpu_ops structure contains a lot of function pointers. It
is a good idea to verify that the function pointer is not NULL
before executing it.

This pa

lib: cpus: sanity check pointers before use

The cpu_ops structure contains a lot of function pointers. It
is a good idea to verify that the function pointer is not NULL
before executing it.

This patch sanity checks each pointer before use to prevent any
unforeseen crashes. These checks have been enabled for debug
builds only.

Change-Id: Ib208331c20e60f0c7c582a20eb3d8cc40fb99d21
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "Revert "libc/memset: Implement function in assembler"" into integration

Revert "libc/memset: Implement function in assembler"

This reverts commit e7d344de01ad11b856233634717aafe9312697e4.
This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware

Revert "libc/memset: Implement function in assembler"

This reverts commit e7d344de01ad11b856233634717aafe9312697e4.
This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge. The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done. This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch.

Change-Id: Iae5f6403c93ac13ceeda29463883fcd4c437f2b7

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Merge changes from topic "at_errata_fix" into integration

* changes:
doc: Update description for AT speculative workaround
lib/cpus: Report AT speculative erratum workaround
Add wrapper for AT

Merge changes from topic "at_errata_fix" into integration

* changes:
doc: Update description for AT speculative workaround
lib/cpus: Report AT speculative erratum workaround
Add wrapper for AT instruction

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libc/memset: Implement function in assembler

Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATI

libc/memset: Implement function in assembler

Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.84% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 24.84%.
- Number of CPU instructions executed during TF-A
boot stage before start of BL33 in RELEASE builds:
----------------------------------------------
| Arch | C | assembler | % |
----------------------------------------------
| Aarch32 | 2073275460 | 1487400003 | -28.25 |
| Aarch64 | 2056807158 | 1244898303 | -39.47 |
----------------------------------------------
The patch also replaces memset.c with aarch64/memset.S
in plat\nvidia\tegra\platform.mk.

Change-Id: Ifbf085a2f577a25491e2d28446ee95a4ac891597
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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SPM: Change condition on saving/restoring EL2 registers

Make this more scalable by explicitly checking internal and hardware
states at run_time

Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Ch

SPM: Change condition on saving/restoring EL2 registers

Make this more scalable by explicitly checking internal and hardware
states at run_time

Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: I1c6ed1c1badb3538a93bff3ac5b5189b59cccfa1

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runtime_exceptions: Update AT speculative workaround

As per latest mailing communication [1], we decided to
update AT speculative workaround implementation in order to
disable page table walk for lo

runtime_exceptions: Update AT speculative workaround

As per latest mailing communication [1], we decided to
update AT speculative workaround implementation in order to
disable page table walk for lower ELs(EL1 or EL0) immediately
after context switching to EL3 from lower ELs.

Previous implementation of AT speculative workaround is available
here: 45aecff00

AT speculative workaround is updated as below:
1. Avoid saving and restoring of SCTLR and TCR registers for EL1
in context save and restore routine respectively.
2. On EL3 entry, save SCTLR and TCR registers for EL1.
3. On EL3 entry, update EL1 system registers to disable stage 1
page table walk for lower ELs (EL1 and EL0) and enable EL1
MMU.
4. On EL3 exit, restore SCTLR and TCR registers for EL1 which
are saved in step 2.

[1]:
https://lists.trustedfirmware.org/pipermail/tf-a/2020-July/000586.html

Change-Id: Iee8de16f81dc970a8f492726f2ddd57e7bd9ffb5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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lib/cpus: Report AT speculative erratum workaround

Reported the status (applies, missing) of AT speculative workaround
which is applicable for below CPUs.

+---------+--------------+
| Errata |

lib/cpus: Report AT speculative erratum workaround

Reported the status (applies, missing) of AT speculative workaround
which is applicable for below CPUs.

+---------+--------------+
| Errata | CPU |
+=========+==============+
| 1165522 | Cortex-A76 |
+---------+--------------+
| 1319367 | Cortex-A72 |
+---------+--------------+
| 1319537 | Cortex-A57 |
+---------+--------------+
| 1530923 | Cortex-A55 |
+---------+--------------+
| 1530924 | Cortex-A53 |
+---------+--------------+

Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT'
if AT speculative errata workaround is enabled for any of the above
CPUs using 'ERRATA_*' CPU specific build macro.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b

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