1/* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Neoverse V1 Errata #1774420. 26 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_neoverse_v1_1774420_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1774420 35 cbz x0, 1f 36 37 /* Set bit 53 in CPUECTLR_EL1 */ 38 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 39 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 40 msr NEOVERSE_V1_CPUECTLR_EL1, x1 41 isb 421: 43 ret x17 44endfunc errata_neoverse_v1_1774420_wa 45 46func check_errata_1774420 47 /* Applies to r0p0 and r1p0. */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1774420 51 52 /* -------------------------------------------------- 53 * Errata Workaround for Neoverse V1 Errata #1791573. 54 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 55 * x0: variant[4:7] and revision[0:3] of current cpu. 56 * Shall clobber: x0-x17 57 * -------------------------------------------------- 58 */ 59func errata_neoverse_v1_1791573_wa 60 /* Check workaround compatibility. */ 61 mov x17, x30 62 bl check_errata_1791573 63 cbz x0, 1f 64 65 /* Set bit 2 in ACTLR2_EL1 */ 66 mrs x1, NEOVERSE_V1_ACTLR2_EL1 67 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 68 msr NEOVERSE_V1_ACTLR2_EL1, x1 69 isb 701: 71 ret x17 72endfunc errata_neoverse_v1_1791573_wa 73 74func check_errata_1791573 75 /* Applies to r0p0 and r1p0. */ 76 mov x1, #0x10 77 b cpu_rev_var_ls 78endfunc check_errata_1791573 79 80 /* -------------------------------------------------- 81 * Errata Workaround for Neoverse V1 Errata #1852267. 82 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 83 * x0: variant[4:7] and revision[0:3] of current cpu. 84 * Shall clobber: x0-x17 85 * -------------------------------------------------- 86 */ 87func errata_neoverse_v1_1852267_wa 88 /* Check workaround compatibility. */ 89 mov x17, x30 90 bl check_errata_1852267 91 cbz x0, 1f 92 93 /* Set bit 28 in ACTLR2_EL1 */ 94 mrs x1, NEOVERSE_V1_ACTLR2_EL1 95 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 96 msr NEOVERSE_V1_ACTLR2_EL1, x1 97 isb 981: 99 ret x17 100endfunc errata_neoverse_v1_1852267_wa 101 102func check_errata_1852267 103 /* Applies to r0p0 and r1p0. */ 104 mov x1, #0x10 105 b cpu_rev_var_ls 106endfunc check_errata_1852267 107 108 /* -------------------------------------------------- 109 * Errata Workaround for Neoverse V1 Errata #1925756. 110 * This applies to revisions <= r1p1. 111 * x0: variant[4:7] and revision[0:3] of current cpu. 112 * Shall clobber: x0-x17 113 * -------------------------------------------------- 114 */ 115func errata_neoverse_v1_1925756_wa 116 /* Check workaround compatibility. */ 117 mov x17, x30 118 bl check_errata_1925756 119 cbz x0, 1f 120 121 /* Set bit 8 in CPUECTLR_EL1 */ 122 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 123 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8 124 msr NEOVERSE_V1_CPUECTLR_EL1, x1 125 isb 1261: 127 ret x17 128endfunc errata_neoverse_v1_1925756_wa 129 130func check_errata_1925756 131 /* Applies to <= r1p1. */ 132 mov x1, #0x11 133 b cpu_rev_var_ls 134endfunc check_errata_1925756 135 136 /* -------------------------------------------------- 137 * Errata Workaround for Neoverse V1 Erratum #1940577 138 * This applies to revisions r1p0 - r1p1 and is open. 139 * It also exists in r0p0 but there is no fix in that 140 * revision. 141 * Inputs: 142 * x0: variant[4:7] and revision[0:3] of current cpu. 143 * Shall clobber: x0-x17 144 * -------------------------------------------------- 145 */ 146func errata_neoverse_v1_1940577_wa 147 /* Compare x0 against revisions r1p0 - r1p1 */ 148 mov x17, x30 149 bl check_errata_1940577 150 cbz x0, 1f 151 152 mov x0, #0 153 msr S3_6_C15_C8_0, x0 154 ldr x0, =0x10E3900002 155 msr S3_6_C15_C8_2, x0 156 ldr x0, =0x10FFF00083 157 msr S3_6_C15_C8_3, x0 158 ldr x0, =0x2001003FF 159 msr S3_6_C15_C8_1, x0 160 161 mov x0, #1 162 msr S3_6_C15_C8_0, x0 163 ldr x0, =0x10E3800082 164 msr S3_6_C15_C8_2, x0 165 ldr x0, =0x10FFF00083 166 msr S3_6_C15_C8_3, x0 167 ldr x0, =0x2001003FF 168 msr S3_6_C15_C8_1, x0 169 170 mov x0, #2 171 msr S3_6_C15_C8_0, x0 172 ldr x0, =0x10E3800200 173 msr S3_6_C15_C8_2, x0 174 ldr x0, =0x10FFF003E0 175 msr S3_6_C15_C8_3, x0 176 ldr x0, =0x2001003FF 177 msr S3_6_C15_C8_1, x0 178 179 isb 1801: 181 ret x17 182endfunc errata_neoverse_v1_1940577_wa 183 184func check_errata_1940577 185 /* Applies to revisions r1p0 - r1p1. */ 186 mov x1, #0x10 187 mov x2, #0x11 188 b cpu_rev_var_range 189endfunc check_errata_1940577 190 191 /* --------------------------------------------- 192 * HW will do the cache maintenance while powering down 193 * --------------------------------------------- 194 */ 195func neoverse_v1_core_pwr_dwn 196 /* --------------------------------------------- 197 * Enable CPU power down bit in power control register 198 * --------------------------------------------- 199 */ 200 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 201 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 202 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 203 isb 204 ret 205endfunc neoverse_v1_core_pwr_dwn 206 207 /* 208 * Errata printing function for Neoverse V1. Must follow AAPCS. 209 */ 210#if REPORT_ERRATA 211func neoverse_v1_errata_report 212 stp x8, x30, [sp, #-16]! 213 214 bl cpu_get_rev_var 215 mov x8, x0 216 217 /* 218 * Report all errata. The revision-variant information is passed to 219 * checking functions of each errata. 220 */ 221 report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 222 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 223 report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 224 report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 225 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 226 227 ldp x8, x30, [sp], #16 228 ret 229endfunc neoverse_v1_errata_report 230#endif 231 232func neoverse_v1_reset_func 233 mov x19, x30 234 235 /* Disable speculative loads */ 236 msr SSBS, xzr 237 isb 238 239#if ERRATA_V1_1774420 240 mov x0, x18 241 bl errata_neoverse_v1_1774420_wa 242#endif 243 244#if ERRATA_V1_1791573 245 mov x0, x18 246 bl errata_neoverse_v1_1791573_wa 247#endif 248 249#if ERRATA_V1_1852267 250 mov x0, x18 251 bl errata_neoverse_v1_1852267_wa 252#endif 253 254#if ERRATA_V1_1925756 255 mov x0, x18 256 bl errata_neoverse_v1_1925756_wa 257#endif 258 259#if ERRATA_V1_1940577 260 mov x0, x18 261 bl errata_neoverse_v1_1940577_wa 262#endif 263 264 ret x19 265endfunc neoverse_v1_reset_func 266 267 /* --------------------------------------------- 268 * This function provides Neoverse-V1 specific 269 * register information for crash reporting. 270 * It needs to return with x6 pointing to 271 * a list of register names in ascii and 272 * x8 - x15 having values of registers to be 273 * reported. 274 * --------------------------------------------- 275 */ 276.section .rodata.neoverse_v1_regs, "aS" 277neoverse_v1_regs: /* The ascii list of register names to be reported */ 278 .asciz "cpuectlr_el1", "" 279 280func neoverse_v1_cpu_reg_dump 281 adr x6, neoverse_v1_regs 282 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 283 ret 284endfunc neoverse_v1_cpu_reg_dump 285 286declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 287 neoverse_v1_reset_func, \ 288 neoverse_v1_core_pwr_dwn 289