1 /* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_V1_H 8 #define NEOVERSE_V1_H 9 10 #define NEOVERSE_V1_MIDR U(0x410FD400) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions. 14 ******************************************************************************/ 15 #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 16 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) 17 18 /******************************************************************************* 19 * CPU Power Control register specific definitions 20 ******************************************************************************/ 21 #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22 #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 23 24 /******************************************************************************* 25 * CPU Auxiliary Control register specific definitions. 26 ******************************************************************************/ 27 #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 28 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 29 30 #endif /* NEOVERSE_V1_H */ 31