1/* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Neoverse V1 Errata #1774420. 26 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_neoverse_v1_1774420_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1774420 35 cbz x0, 1f 36 37 /* Set bit 53 in CPUECTLR_EL1 */ 38 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 39 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 40 msr NEOVERSE_V1_CPUECTLR_EL1, x1 41 isb 421: 43 ret x17 44endfunc errata_neoverse_v1_1774420_wa 45 46func check_errata_1774420 47 /* Applies to r0p0 and r1p0. */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1774420 51 52 /* -------------------------------------------------- 53 * Errata Workaround for Neoverse V1 Errata #1791573. 54 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 55 * x0: variant[4:7] and revision[0:3] of current cpu. 56 * Shall clobber: x0-x17 57 * -------------------------------------------------- 58 */ 59func errata_neoverse_v1_1791573_wa 60 /* Check workaround compatibility. */ 61 mov x17, x30 62 bl check_errata_1791573 63 cbz x0, 1f 64 65 /* Set bit 2 in ACTLR2_EL1 */ 66 mrs x1, NEOVERSE_V1_ACTLR2_EL1 67 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 68 msr NEOVERSE_V1_ACTLR2_EL1, x1 69 isb 701: 71 ret x17 72endfunc errata_neoverse_v1_1791573_wa 73 74func check_errata_1791573 75 /* Applies to r0p0 and r1p0. */ 76 mov x1, #0x10 77 b cpu_rev_var_ls 78endfunc check_errata_1791573 79 80 /* -------------------------------------------------- 81 * Errata Workaround for Neoverse V1 Erratum #1940577 82 * This applies to revisions r1p0 - r1p1 and is open. 83 * It also exists in r0p0 but there is no fix in that 84 * revision. 85 * Inputs: 86 * x0: variant[4:7] and revision[0:3] of current cpu. 87 * Shall clobber: x0-x17 88 * -------------------------------------------------- 89 */ 90func errata_neoverse_v1_1940577_wa 91 /* Compare x0 against revisions r1p0 - r1p1 */ 92 mov x17, x30 93 bl check_errata_1940577 94 cbz x0, 1f 95 96 mov x0, #0 97 msr S3_6_C15_C8_0, x0 98 ldr x0, =0x10E3900002 99 msr S3_6_C15_C8_2, x0 100 ldr x0, =0x10FFF00083 101 msr S3_6_C15_C8_3, x0 102 ldr x0, =0x2001003FF 103 msr S3_6_C15_C8_1, x0 104 105 mov x0, #1 106 msr S3_6_C15_C8_0, x0 107 ldr x0, =0x10E3800082 108 msr S3_6_C15_C8_2, x0 109 ldr x0, =0x10FFF00083 110 msr S3_6_C15_C8_3, x0 111 ldr x0, =0x2001003FF 112 msr S3_6_C15_C8_1, x0 113 114 mov x0, #2 115 msr S3_6_C15_C8_0, x0 116 ldr x0, =0x10E3800200 117 msr S3_6_C15_C8_2, x0 118 ldr x0, =0x10FFF003E0 119 msr S3_6_C15_C8_3, x0 120 ldr x0, =0x2001003FF 121 msr S3_6_C15_C8_1, x0 122 123 isb 1241: 125 ret x17 126endfunc errata_neoverse_v1_1940577_wa 127 128func check_errata_1940577 129 /* Applies to revisions r1p0 - r1p1. */ 130 mov x1, #0x10 131 mov x2, #0x11 132 b cpu_rev_var_range 133endfunc check_errata_1940577 134 135 /* --------------------------------------------- 136 * HW will do the cache maintenance while powering down 137 * --------------------------------------------- 138 */ 139func neoverse_v1_core_pwr_dwn 140 /* --------------------------------------------- 141 * Enable CPU power down bit in power control register 142 * --------------------------------------------- 143 */ 144 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 145 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 146 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 147 isb 148 ret 149endfunc neoverse_v1_core_pwr_dwn 150 151 /* 152 * Errata printing function for Neoverse V1. Must follow AAPCS. 153 */ 154#if REPORT_ERRATA 155func neoverse_v1_errata_report 156 stp x8, x30, [sp, #-16]! 157 158 bl cpu_get_rev_var 159 mov x8, x0 160 161 /* 162 * Report all errata. The revision-variant information is passed to 163 * checking functions of each errata. 164 */ 165 report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 166 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 167 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 168 169 ldp x8, x30, [sp], #16 170 ret 171endfunc neoverse_v1_errata_report 172#endif 173 174func neoverse_v1_reset_func 175 mov x19, x30 176 177 /* Disable speculative loads */ 178 msr SSBS, xzr 179 isb 180 181#if ERRATA_V1_1774420 182 mov x0, x18 183 bl errata_neoverse_v1_1774420_wa 184#endif 185 186#if ERRATA_V1_1791573 187 mov x0, x18 188 bl errata_neoverse_v1_1791573_wa 189#endif 190 191#if ERRATA_V1_1940577 192 mov x0, x18 193 bl errata_neoverse_v1_1940577_wa 194#endif 195 196 ret x19 197endfunc neoverse_v1_reset_func 198 199 /* --------------------------------------------- 200 * This function provides Neoverse-V1 specific 201 * register information for crash reporting. 202 * It needs to return with x6 pointing to 203 * a list of register names in ascii and 204 * x8 - x15 having values of registers to be 205 * reported. 206 * --------------------------------------------- 207 */ 208.section .rodata.neoverse_v1_regs, "aS" 209neoverse_v1_regs: /* The ascii list of register names to be reported */ 210 .asciz "cpuectlr_el1", "" 211 212func neoverse_v1_cpu_reg_dump 213 adr x6, neoverse_v1_regs 214 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 215 ret 216endfunc neoverse_v1_cpu_reg_dump 217 218declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 219 neoverse_v1_reset_func, \ 220 neoverse_v1_core_pwr_dwn 221