1/* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Neoverse V1 Errata #1774420. 26 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_neoverse_v1_1774420_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1774420 35 cbz x0, 1f 36 37 /* Set bit 53 in CPUECTLR_EL1 */ 38 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 39 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 40 msr NEOVERSE_V1_CPUECTLR_EL1, x1 41 isb 421: 43 ret x17 44endfunc errata_neoverse_v1_1774420_wa 45 46func check_errata_1774420 47 /* Applies to r0p0 and r1p0. */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1774420 51 52 /* -------------------------------------------------- 53 * Errata Workaround for Neoverse V1 Errata #1791573. 54 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 55 * x0: variant[4:7] and revision[0:3] of current cpu. 56 * Shall clobber: x0-x17 57 * -------------------------------------------------- 58 */ 59func errata_neoverse_v1_1791573_wa 60 /* Check workaround compatibility. */ 61 mov x17, x30 62 bl check_errata_1791573 63 cbz x0, 1f 64 65 /* Set bit 2 in ACTLR2_EL1 */ 66 mrs x1, NEOVERSE_V1_ACTLR2_EL1 67 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 68 msr NEOVERSE_V1_ACTLR2_EL1, x1 69 isb 701: 71 ret x17 72endfunc errata_neoverse_v1_1791573_wa 73 74func check_errata_1791573 75 /* Applies to r0p0 and r1p0. */ 76 mov x1, #0x10 77 b cpu_rev_var_ls 78endfunc check_errata_1791573 79 80 /* -------------------------------------------------- 81 * Errata Workaround for Neoverse V1 Errata #1852267. 82 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 83 * x0: variant[4:7] and revision[0:3] of current cpu. 84 * Shall clobber: x0-x17 85 * -------------------------------------------------- 86 */ 87func errata_neoverse_v1_1852267_wa 88 /* Check workaround compatibility. */ 89 mov x17, x30 90 bl check_errata_1852267 91 cbz x0, 1f 92 93 /* Set bit 28 in ACTLR2_EL1 */ 94 mrs x1, NEOVERSE_V1_ACTLR2_EL1 95 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 96 msr NEOVERSE_V1_ACTLR2_EL1, x1 97 isb 981: 99 ret x17 100endfunc errata_neoverse_v1_1852267_wa 101 102func check_errata_1852267 103 /* Applies to r0p0 and r1p0. */ 104 mov x1, #0x10 105 b cpu_rev_var_ls 106endfunc check_errata_1852267 107 108 /* -------------------------------------------------- 109 * Errata Workaround for Neoverse V1 Erratum #1940577 110 * This applies to revisions r1p0 - r1p1 and is open. 111 * It also exists in r0p0 but there is no fix in that 112 * revision. 113 * Inputs: 114 * x0: variant[4:7] and revision[0:3] of current cpu. 115 * Shall clobber: x0-x17 116 * -------------------------------------------------- 117 */ 118func errata_neoverse_v1_1940577_wa 119 /* Compare x0 against revisions r1p0 - r1p1 */ 120 mov x17, x30 121 bl check_errata_1940577 122 cbz x0, 1f 123 124 mov x0, #0 125 msr S3_6_C15_C8_0, x0 126 ldr x0, =0x10E3900002 127 msr S3_6_C15_C8_2, x0 128 ldr x0, =0x10FFF00083 129 msr S3_6_C15_C8_3, x0 130 ldr x0, =0x2001003FF 131 msr S3_6_C15_C8_1, x0 132 133 mov x0, #1 134 msr S3_6_C15_C8_0, x0 135 ldr x0, =0x10E3800082 136 msr S3_6_C15_C8_2, x0 137 ldr x0, =0x10FFF00083 138 msr S3_6_C15_C8_3, x0 139 ldr x0, =0x2001003FF 140 msr S3_6_C15_C8_1, x0 141 142 mov x0, #2 143 msr S3_6_C15_C8_0, x0 144 ldr x0, =0x10E3800200 145 msr S3_6_C15_C8_2, x0 146 ldr x0, =0x10FFF003E0 147 msr S3_6_C15_C8_3, x0 148 ldr x0, =0x2001003FF 149 msr S3_6_C15_C8_1, x0 150 151 isb 1521: 153 ret x17 154endfunc errata_neoverse_v1_1940577_wa 155 156func check_errata_1940577 157 /* Applies to revisions r1p0 - r1p1. */ 158 mov x1, #0x10 159 mov x2, #0x11 160 b cpu_rev_var_range 161endfunc check_errata_1940577 162 163 /* --------------------------------------------- 164 * HW will do the cache maintenance while powering down 165 * --------------------------------------------- 166 */ 167func neoverse_v1_core_pwr_dwn 168 /* --------------------------------------------- 169 * Enable CPU power down bit in power control register 170 * --------------------------------------------- 171 */ 172 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 173 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 174 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 175 isb 176 ret 177endfunc neoverse_v1_core_pwr_dwn 178 179 /* 180 * Errata printing function for Neoverse V1. Must follow AAPCS. 181 */ 182#if REPORT_ERRATA 183func neoverse_v1_errata_report 184 stp x8, x30, [sp, #-16]! 185 186 bl cpu_get_rev_var 187 mov x8, x0 188 189 /* 190 * Report all errata. The revision-variant information is passed to 191 * checking functions of each errata. 192 */ 193 report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 194 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 195 report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 196 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 197 198 ldp x8, x30, [sp], #16 199 ret 200endfunc neoverse_v1_errata_report 201#endif 202 203func neoverse_v1_reset_func 204 mov x19, x30 205 206 /* Disable speculative loads */ 207 msr SSBS, xzr 208 isb 209 210#if ERRATA_V1_1774420 211 mov x0, x18 212 bl errata_neoverse_v1_1774420_wa 213#endif 214 215#if ERRATA_V1_1791573 216 mov x0, x18 217 bl errata_neoverse_v1_1791573_wa 218#endif 219 220#if ERRATA_V1_1852267 221 mov x0, x18 222 bl errata_neoverse_v1_1852267_wa 223#endif 224 225#if ERRATA_V1_1940577 226 mov x0, x18 227 bl errata_neoverse_v1_1940577_wa 228#endif 229 230 ret x19 231endfunc neoverse_v1_reset_func 232 233 /* --------------------------------------------- 234 * This function provides Neoverse-V1 specific 235 * register information for crash reporting. 236 * It needs to return with x6 pointing to 237 * a list of register names in ascii and 238 * x8 - x15 having values of registers to be 239 * reported. 240 * --------------------------------------------- 241 */ 242.section .rodata.neoverse_v1_regs, "aS" 243neoverse_v1_regs: /* The ascii list of register names to be reported */ 244 .asciz "cpuectlr_el1", "" 245 246func neoverse_v1_cpu_reg_dump 247 adr x6, neoverse_v1_regs 248 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 249 ret 250endfunc neoverse_v1_cpu_reg_dump 251 252declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 253 neoverse_v1_reset_func, \ 254 neoverse_v1_core_pwr_dwn 255