| ccbec91c | 24-Feb-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for EL3 won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI tw
Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for EL3 won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time.
Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision.
This errata has been enabled for Juno.
The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround.
Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| f10644c5 | 13-Feb-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Improve debug output of the translation tables
The printed output has been improved in two ways:
- Whenever multiple invalid descriptors are found, only the first one is printed, and a line is ad
Improve debug output of the translation tables
The printed output has been improved in two ways:
- Whenever multiple invalid descriptors are found, only the first one is printed, and a line is added to inform about how many descriptors have been omitted.
- At the beginning of each line there is an indication of the table level the entry belongs to. Example of the new output: `[LV3] VA:0x1000 PA:0x1000 size:0x1000 MEM-RO-S-EXEC`
Change-Id: Ib6f1cd8dbd449452f09258f4108241eb11f8d445 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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