1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl31.h> 35 #include <bl_common.h> 36 #include <console.h> 37 #include <cortex_a57.h> 38 #include <cortex_a53.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <errno.h> 42 #include <memctrl.h> 43 #include <mmio.h> 44 #include <platform.h> 45 #include <platform_def.h> 46 #include <stddef.h> 47 #include <string.h> 48 #include <tegra_def.h> 49 #include <tegra_private.h> 50 51 extern void zeromem16(void *mem, unsigned int length); 52 53 /******************************************************************************* 54 * Declarations of linker defined symbols which will help us find the layout 55 * of trusted SRAM 56 ******************************************************************************/ 57 extern unsigned long __TEXT_START__; 58 extern unsigned long __TEXT_END__; 59 extern unsigned long __RW_START__; 60 extern unsigned long __RW_END__; 61 extern unsigned long __RODATA_START__; 62 extern unsigned long __RODATA_END__; 63 extern unsigned long __BL31_END__; 64 65 extern uint64_t tegra_bl31_phys_base; 66 extern uint64_t tegra_console_base; 67 68 /* 69 * The next 3 constants identify the extents of the code, RO data region and the 70 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 71 * therefore they must be page-aligned. It is the responsibility of the linker 72 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 73 * refer to page-aligned addresses. 74 */ 75 #define BL31_RW_START (unsigned long)(&__RW_START__) 76 #define BL31_RW_END (unsigned long)(&__RW_END__) 77 #define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__) 78 #define BL31_RODATA_END (unsigned long)(&__RODATA_END__) 79 #define BL31_END (unsigned long)(&__BL31_END__) 80 81 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 82 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 83 .tzdram_size = (uint64_t)TZDRAM_SIZE 84 }; 85 86 /******************************************************************************* 87 * This variable holds the non-secure image entry address 88 ******************************************************************************/ 89 extern uint64_t ns_image_entrypoint; 90 91 /******************************************************************************* 92 * The following platform setup functions are weakly defined. They 93 * provide typical implementations that will be overridden by a SoC. 94 ******************************************************************************/ 95 #pragma weak plat_early_platform_setup 96 #pragma weak plat_get_bl31_params 97 #pragma weak plat_get_bl31_plat_params 98 99 void plat_early_platform_setup(void) 100 { 101 ; /* do nothing */ 102 } 103 104 bl31_params_t *plat_get_bl31_params(void) 105 { 106 return NULL; 107 } 108 109 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 110 { 111 return NULL; 112 } 113 114 /******************************************************************************* 115 * Return a pointer to the 'entry_point_info' structure of the next image for 116 * security state specified. BL33 corresponds to the non-secure image type 117 * while BL32 corresponds to the secure image type. 118 ******************************************************************************/ 119 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 120 { 121 if (type == NON_SECURE) 122 return &bl33_image_ep_info; 123 124 /* return BL32 entry point info if it is valid */ 125 if (type == SECURE && bl32_image_ep_info.pc) 126 return &bl32_image_ep_info; 127 128 return NULL; 129 } 130 131 /******************************************************************************* 132 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 133 * passes this platform specific information. 134 ******************************************************************************/ 135 plat_params_from_bl2_t *bl31_get_plat_params(void) 136 { 137 return &plat_bl31_params_from_bl2; 138 } 139 140 /******************************************************************************* 141 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 142 * info. 143 ******************************************************************************/ 144 void bl31_early_platform_setup(bl31_params_t *from_bl2, 145 void *plat_params_from_bl2) 146 { 147 plat_params_from_bl2_t *plat_params = 148 (plat_params_from_bl2_t *)plat_params_from_bl2; 149 #if DEBUG 150 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 151 #endif 152 image_info_t bl32_img_info = { {0} }; 153 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 154 155 /* 156 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 157 * there's no argument to relay from a previous bootloader. Platforms 158 * might use custom ways to get arguments, so provide handlers which 159 * they can override. 160 */ 161 if (from_bl2 == NULL) 162 from_bl2 = plat_get_bl31_params(); 163 if (plat_params == NULL) 164 plat_params = plat_get_bl31_plat_params(); 165 166 /* 167 * Copy BL3-3, BL3-2 entry point information. 168 * They are stored in Secure RAM, in BL2's address space. 169 */ 170 assert(from_bl2); 171 assert(from_bl2->bl33_ep_info); 172 bl33_image_ep_info = *from_bl2->bl33_ep_info; 173 174 if (from_bl2->bl32_ep_info) 175 bl32_image_ep_info = *from_bl2->bl32_ep_info; 176 177 /* 178 * Parse platform specific parameters - TZDRAM aperture base and size 179 */ 180 assert(plat_params); 181 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 182 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 183 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 184 185 /* 186 * It is very important that we run either from TZDRAM or TZSRAM base. 187 * Add an explicit check here. 188 */ 189 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 190 (TEGRA_TZRAM_BASE != BL31_BASE)) 191 panic(); 192 193 /* 194 * Get the base address of the UART controller to be used for the 195 * console 196 */ 197 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 198 199 if (tegra_console_base != (uint64_t)0) { 200 /* 201 * Configure the UART port to be used as the console 202 */ 203 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 204 TEGRA_CONSOLE_BAUDRATE); 205 } 206 207 /* 208 * Do initial security configuration to allow DRAM/device access. 209 */ 210 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 211 plat_bl31_params_from_bl2.tzdram_size); 212 213 /* 214 * The previous bootloader might not have placed the BL32 image 215 * inside the TZDRAM. We check the BL32 image info to find out 216 * the base/PC values and relocate the image if necessary. 217 */ 218 if (from_bl2->bl32_image_info) { 219 220 bl32_img_info = *from_bl2->bl32_image_info; 221 222 /* Relocate BL32 if it resides outside of the TZDRAM */ 223 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 224 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 225 plat_bl31_params_from_bl2.tzdram_size; 226 bl32_start = bl32_img_info.image_base; 227 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 228 229 assert(tzdram_end > tzdram_start); 230 assert(bl32_end > bl32_start); 231 assert(bl32_image_ep_info.pc > tzdram_start); 232 assert(bl32_image_ep_info.pc < tzdram_end); 233 234 /* relocate BL32 */ 235 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) { 236 237 INFO("Relocate BL32 to TZDRAM\n"); 238 239 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 240 (void *)(uintptr_t)bl32_start, 241 bl32_img_info.image_size); 242 243 /* clean up non-secure intermediate buffer */ 244 zeromem16((void *)(uintptr_t)bl32_start, 245 bl32_img_info.image_size); 246 } 247 } 248 249 /* Early platform setup for Tegra SoCs */ 250 plat_early_platform_setup(); 251 252 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? 253 "Denver" : "ARM", read_mpidr()); 254 } 255 256 /******************************************************************************* 257 * Initialize the gic, configure the SCR. 258 ******************************************************************************/ 259 void bl31_platform_setup(void) 260 { 261 uint32_t tmp_reg; 262 263 /* Initialize the gic cpu and distributor interfaces */ 264 plat_gic_setup(); 265 266 /* 267 * Initialize delay timer 268 */ 269 tegra_delay_timer_init(); 270 271 /* 272 * Setup secondary CPU POR infrastructure. 273 */ 274 plat_secondary_setup(); 275 276 /* 277 * Initial Memory Controller configuration. 278 */ 279 tegra_memctrl_setup(); 280 281 /* 282 * Set up the TZRAM memory aperture to allow only secure world 283 * access 284 */ 285 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 286 287 /* Set the next EL to be AArch64 */ 288 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 289 write_scr(tmp_reg); 290 291 INFO("BL3-1: Tegra platform setup complete\n"); 292 } 293 294 /******************************************************************************* 295 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 296 ******************************************************************************/ 297 void bl31_plat_runtime_setup(void) 298 { 299 /* 300 * During boot, USB3 and flash media (SDMMC/SATA) devices need 301 * access to IRAM. Because these clients connect to the MC and 302 * do not have a direct path to the IRAM, the MC implements AHB 303 * redirection during boot to allow path to IRAM. In this mode 304 * accesses to a programmed memory address aperture are directed 305 * to the AHB bus, allowing access to the IRAM. This mode must be 306 * disabled before we jump to the non-secure world. 307 */ 308 tegra_memctrl_disable_ahb_redirection(); 309 } 310 311 /******************************************************************************* 312 * Perform the very early platform specific architectural setup here. At the 313 * moment this only intializes the mmu in a quick and dirty way. 314 ******************************************************************************/ 315 void bl31_plat_arch_setup(void) 316 { 317 unsigned long rw_start = BL31_RW_START; 318 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 319 unsigned long rodata_start = BL31_RODATA_BASE; 320 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 321 unsigned long code_base = (unsigned long)(&__TEXT_START__); 322 unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base; 323 const mmap_region_t *plat_mmio_map = NULL; 324 #if USE_COHERENT_MEM 325 unsigned long coh_start, coh_size; 326 #endif 327 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 328 329 /* add memory regions */ 330 mmap_add_region(rw_start, rw_start, 331 rw_size, 332 MT_MEMORY | MT_RW | MT_SECURE); 333 mmap_add_region(rodata_start, rodata_start, 334 rodata_size, 335 MT_RO_DATA | MT_SECURE); 336 mmap_add_region(code_base, code_base, 337 code_size, 338 MT_CODE | MT_SECURE); 339 340 /* map TZDRAM used by BL31 as coherent memory */ 341 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 342 mmap_add_region(params_from_bl2->tzdram_base, 343 params_from_bl2->tzdram_base, 344 BL31_SIZE, 345 MT_DEVICE | MT_RW | MT_SECURE); 346 } 347 348 #if USE_COHERENT_MEM 349 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 350 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 351 352 mmap_add_region(coh_start, coh_start, 353 coh_size, 354 MT_DEVICE | MT_RW | MT_SECURE); 355 #endif 356 357 /* add MMIO space */ 358 plat_mmio_map = plat_get_mmio_map(); 359 if (plat_mmio_map) 360 mmap_add(plat_mmio_map); 361 else 362 WARN("MMIO map not available\n"); 363 364 /* set up translation tables */ 365 init_xlat_tables(); 366 367 /* enable the MMU */ 368 enable_mmu_el3(0); 369 370 INFO("BL3-1: Tegra: MMU enabled\n"); 371 } 372 373 /******************************************************************************* 374 * Check if the given NS DRAM range is valid 375 ******************************************************************************/ 376 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 377 { 378 uint64_t end = base + size_in_bytes - 1; 379 380 /* 381 * Check if the NS DRAM address is valid 382 */ 383 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || 384 (base >= end)) { 385 ERROR("NS address is out-of-bounds!\n"); 386 return -EFAULT; 387 } 388 389 /* 390 * TZDRAM aperture contains the BL31 and BL32 images, so we need 391 * to check if the NS DRAM range overlaps the TZDRAM aperture. 392 */ 393 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 394 ERROR("NS address overlaps TZDRAM!\n"); 395 return -ENOTSUP; 396 } 397 398 /* valid NS address */ 399 return 0; 400 } 401