1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <mce.h> 34 #include <mmio.h> 35 #include <string.h> 36 #include <tegra_def.h> 37 #include <tegra_private.h> 38 39 #define MISCREG_CPU_RESET_VECTOR 0x2000 40 #define MISCREG_AA64_RST_LOW 0x2004 41 #define MISCREG_AA64_RST_HIGH 0x2008 42 43 #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658 44 #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C 45 46 #define CPU_RESET_MODE_AA64 1 47 48 extern uint64_t tegra_bl31_phys_base; 49 extern uint64_t __tegra186_cpu_reset_handler_end; 50 51 /******************************************************************************* 52 * Setup secondary CPU vectors 53 ******************************************************************************/ 54 void plat_secondary_setup(void) 55 { 56 uint32_t addr_low, addr_high; 57 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 58 uint64_t cpu_reset_handler_base; 59 60 INFO("Setting up secondary CPU boot\n"); 61 62 if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) && 63 (tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) { 64 65 /* 66 * The BL31 code resides in the TZSRAM which loses state 67 * when we enter System Suspend. Copy the wakeup trampoline 68 * code to TZDRAM to help us exit from System Suspend. 69 */ 70 cpu_reset_handler_base = params_from_bl2->tzdram_base; 71 memcpy16((void *)((uintptr_t)cpu_reset_handler_base), 72 (void *)(uintptr_t)tegra186_cpu_reset_handler, 73 (uintptr_t)&__tegra186_cpu_reset_handler_end - 74 (uintptr_t)tegra186_cpu_reset_handler); 75 76 } else { 77 cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 78 } 79 80 addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 81 addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); 82 83 /* write lower 32 bits first, then the upper 11 bits */ 84 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 85 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 86 87 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 88 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 89 addr_low); 90 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 91 addr_high); 92 93 /* update reset vector address to the CCPLEX */ 94 mce_update_reset_vector(); 95 } 96