1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context_mgmt.h> 36 #include <debug.h> 37 #include <denver.h> 38 #include <errno.h> 39 #include <mce.h> 40 #include <memctrl.h> 41 #include <runtime_svc.h> 42 #include <t18x_ari.h> 43 #include <tegra_private.h> 44 45 extern uint32_t tegra186_system_powerdn_state; 46 47 /******************************************************************************* 48 * Offset to read the ref_clk counter value 49 ******************************************************************************/ 50 #define REF_CLK_OFFSET 4 51 52 /******************************************************************************* 53 * Tegra186 SiP SMCs 54 ******************************************************************************/ 55 #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01 56 #define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0x82FFFE02 57 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00 58 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01 59 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02 60 #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03 61 #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04 62 #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05 63 #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06 64 #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07 65 #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08 66 #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09 67 #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A 68 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B 69 #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C 70 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D 71 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E 72 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F 73 #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10 74 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11 75 #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12 76 77 /******************************************************************************* 78 * This function is responsible for handling all T186 SiP calls 79 ******************************************************************************/ 80 int plat_sip_handler(uint32_t smc_fid, 81 uint64_t x1, 82 uint64_t x2, 83 uint64_t x3, 84 uint64_t x4, 85 void *cookie, 86 void *handle, 87 uint64_t flags) 88 { 89 int mce_ret; 90 int impl, cpu; 91 uint32_t base, core_clk_ctr, ref_clk_ctr; 92 93 switch (smc_fid) { 94 95 /* 96 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - 97 * 0x82FFFFFF SiP SMC space 98 */ 99 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: 100 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: 101 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: 102 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: 103 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: 104 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: 105 case TEGRA_SIP_MCE_CMD_CC3_CTRL: 106 case TEGRA_SIP_MCE_CMD_ECHO_DATA: 107 case TEGRA_SIP_MCE_CMD_READ_VERSIONS: 108 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: 109 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 110 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: 111 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: 112 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: 113 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: 114 case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: 115 case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: 116 case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: 117 118 /* clean up the high bits */ 119 smc_fid &= MCE_CMD_MASK; 120 121 /* execute the command and store the result */ 122 mce_ret = mce_command_handler(smc_fid, x1, x2, x3); 123 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); 124 125 return 0; 126 127 case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: 128 129 /* clean up the high bits */ 130 x1 = (uint32_t)x1; 131 132 /* 133 * SC8 is a special Tegra186 system state where the CPUs and 134 * DRAM are powered down but the other subsystem is still 135 * alive. 136 */ 137 if ((x1 == TEGRA_ARI_SYSTEM_SC8) || 138 (x1 == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF)) { 139 140 tegra186_system_powerdn_state = x1; 141 flush_dcache_range( 142 (uintptr_t)&tegra186_system_powerdn_state, 143 sizeof(tegra186_system_powerdn_state)); 144 145 } else { 146 147 ERROR("%s: unhandled powerdn state (%d)\n", __func__, 148 (uint32_t)x1); 149 return -ENOTSUP; 150 } 151 152 return 0; 153 154 /* 155 * This function ID reads the Activity monitor's core/ref clock 156 * counter values for a core/cluster. 157 * 158 * x1 = MPIDR of the target core 159 * x2 = MIDR of the target core 160 */ 161 case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS: 162 163 cpu = (uint32_t)x1 & MPIDR_CPU_MASK; 164 impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 165 166 /* sanity check target CPU number */ 167 if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER) 168 return -EINVAL; 169 170 /* get the base address for the current CPU */ 171 base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE : 172 TEGRA_ARM_ACTMON_CTR_BASE; 173 174 /* read the clock counter values */ 175 core_clk_ctr = mmio_read_32(base + (8 * cpu)); 176 ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET); 177 178 /* return the counter values as two different parameters */ 179 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, core_clk_ctr); 180 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, ref_clk_ctr); 181 182 return 0; 183 184 default: 185 break; 186 } 187 188 return -ENOTSUP; 189 } 190