1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __MEMCTRLV2_H__ 32 #define __MEMCTRLV2_H__ 33 34 #include <tegra_def.h> 35 36 #ifndef __ASSEMBLY__ 37 38 #include <sys/types.h> 39 40 /******************************************************************************* 41 * StreamID to indicate no SMMU translations (requests to be steered on the 42 * SMMU bypass path) 43 ******************************************************************************/ 44 #define MC_STREAM_ID_MAX 0x7F 45 46 /******************************************************************************* 47 * Stream ID Override Config registers 48 ******************************************************************************/ 49 #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000 50 #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070 51 #define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8 52 #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0 53 #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0 54 #define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8 55 #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 56 #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 57 #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188 58 #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 59 #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 60 #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 61 #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 62 #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 63 #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 64 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 65 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 66 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 67 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 68 #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 69 #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 70 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 71 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 72 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 73 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308 74 #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 75 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 76 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 77 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328 78 #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 79 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 80 #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 81 #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 82 #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 83 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 84 #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 85 #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 86 #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 87 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 88 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 89 #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 90 #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 91 #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 92 #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 93 #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 94 #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 95 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 96 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 97 #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 98 #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 99 #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 100 #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 101 #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 102 #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 103 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 104 #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 105 #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 106 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 107 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 108 #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 109 #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 110 #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 111 #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 112 #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 113 #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 114 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 115 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 116 #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 117 #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 118 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 119 #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 120 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 121 122 /******************************************************************************* 123 * Macro to calculate Security cfg register addr from StreamID Override register 124 ******************************************************************************/ 125 #define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t)) 126 127 /******************************************************************************* 128 * Memory Controller transaction override config registers 129 ******************************************************************************/ 130 #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 131 #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 132 #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 133 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 134 #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 135 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 136 #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 137 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328 138 #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 139 #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 140 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0 141 #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 142 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 143 #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 144 #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 145 #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 146 #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 147 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 148 #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 149 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 150 #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 151 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308 152 #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 153 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 154 #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 155 #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 156 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8 157 #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 158 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 159 #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 160 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440 161 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 162 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448 163 #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 164 #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 165 #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 166 #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 167 #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 168 #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 169 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 170 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 171 #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 172 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 173 #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 174 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 175 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 176 #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 177 #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 178 #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 179 #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 180 #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 181 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 182 #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 183 #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 184 #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 185 #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 186 #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 187 #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 188 #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 189 #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 190 #define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070 191 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 192 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 193 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 194 #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 195 #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 196 #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 197 #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 198 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 199 #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 200 #define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188 201 #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 202 203 /******************************************************************************* 204 * Structure to hold the transaction override settings to use to override 205 * client inputs 206 ******************************************************************************/ 207 typedef struct mc_txn_override_cfg { 208 uint32_t offset; 209 uint8_t cgid_tag; 210 } mc_txn_override_cfg_t; 211 212 #define mc_make_txn_override_cfg(off, val) \ 213 { \ 214 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ 215 .cgid_tag = MC_TXN_OVERRIDE_ ## val \ 216 } 217 218 /******************************************************************************* 219 * Structure to hold the Stream ID to use to override client inputs 220 ******************************************************************************/ 221 typedef struct mc_streamid_override_cfg { 222 uint32_t offset; 223 uint8_t stream_id; 224 } mc_streamid_override_cfg_t; 225 226 /******************************************************************************* 227 * Structure to hold the Stream ID Security Configuration settings 228 ******************************************************************************/ 229 typedef struct mc_streamid_security_cfg { 230 char *name; 231 uint32_t offset; 232 int override_enable; 233 int override_client_inputs; 234 int override_client_ns_flag; 235 } mc_streamid_security_cfg_t; 236 237 #define OVERRIDE_DISABLE 1 238 #define OVERRIDE_ENABLE 0 239 #define CLIENT_FLAG_SECURE 0 240 #define CLIENT_FLAG_NON_SECURE 1 241 #define CLIENT_INPUTS_OVERRIDE 1 242 #define CLIENT_INPUTS_NO_OVERRIDE 0 243 244 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 245 { \ 246 .name = # off, \ 247 .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \ 248 MC_STREAMID_OVERRIDE_CFG_ ## off), \ 249 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 250 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 251 .override_enable = OVERRIDE_ ## access \ 252 } 253 254 /******************************************************************************* 255 * Structure to hold Memory Controller's Configuration settings 256 ******************************************************************************/ 257 typedef struct tegra_mc_settings { 258 const uint32_t *streamid_override_cfg; 259 uint32_t num_streamid_override_cfgs; 260 const mc_streamid_security_cfg_t *streamid_security_cfg; 261 uint32_t num_streamid_security_cfgs; 262 const mc_txn_override_cfg_t *txn_override_cfg; 263 uint32_t num_txn_override_cfgs; 264 } tegra_mc_settings_t; 265 266 #endif /* __ASSEMBLY__ */ 267 268 /******************************************************************************* 269 * Memory Controller SMMU Bypass config register 270 ******************************************************************************/ 271 #define MC_SMMU_BYPASS_CONFIG 0x1820 272 #define MC_SMMU_BYPASS_CTRL_MASK 0x3 273 #define MC_SMMU_BYPASS_CTRL_SHIFT 0 274 #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT) 275 #define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT) 276 #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT) 277 #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT) 278 #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31) 279 #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 280 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 281 282 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0) 283 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4) 284 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12) 285 286 /******************************************************************************* 287 * Non-SO_DEV transactions override values for CGID_TAG bitfield for the 288 * MC_TXN_OVERRIDE_CONFIG_{module} registers 289 ******************************************************************************/ 290 #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0 291 #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1 292 #define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2 293 #define MC_TXN_OVERRIDE_CGID_TAG_ADR 3 294 #define MC_TXN_OVERRIDE_CGID_TAG_MASK 3 295 296 /******************************************************************************* 297 * Memory Controller Reset Control registers 298 ******************************************************************************/ 299 #define MC_CLIENT_HOTRESET_CTRL0 0x200 300 #define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0 301 #define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1 << 0) 302 #define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1 << 6) 303 #define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1 << 7) 304 #define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1 << 8) 305 #define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1 << 9) 306 #define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1 << 11) 307 #define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1 << 15) 308 #define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1 << 17) 309 #define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1 << 18) 310 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1 << 19) 311 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1 << 20) 312 #define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1 << 22) 313 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1 << 29) 314 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1 << 30) 315 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1 << 31) 316 #define MC_CLIENT_HOTRESET_STATUS0 0x204 317 #define MC_CLIENT_HOTRESET_CTRL1 0x970 318 #define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0 319 #define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1 << 0) 320 #define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1 << 2) 321 #define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1 << 5) 322 #define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1 << 6) 323 #define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1 << 7) 324 #define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1 << 8) 325 #define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1 << 12) 326 #define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1 << 13) 327 #define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1 << 18) 328 #define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1 << 19) 329 #define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1 << 20) 330 #define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1 << 21) 331 #define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1 << 22) 332 #define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1 << 23) 333 #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24) 334 #define MC_CLIENT_HOTRESET_STATUS1 0x974 335 336 /******************************************************************************* 337 * Memory Controller's PCFIFO client configuration registers 338 ******************************************************************************/ 339 #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 340 #define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000 341 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17) 342 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17) 343 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21) 344 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21) 345 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29) 346 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29) 347 348 #define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 349 #define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000 350 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11) 351 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11) 352 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13) 353 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13) 354 355 #define MC_PCFIFO_CLIENT_CONFIG3 0xddc 356 #define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0 357 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7) 358 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7) 359 360 #define MC_PCFIFO_CLIENT_CONFIG4 0xde0 361 #define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0 362 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1) 363 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1) 364 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5) 365 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5) 366 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13) 367 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13) 368 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15) 369 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15) 370 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17) 371 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17) 372 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22) 373 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22) 374 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26) 375 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26) 376 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30) 377 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30) 378 379 #define MC_PCFIFO_CLIENT_CONFIG5 0xbf4 380 #define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0 381 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0) 382 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0) 383 384 /******************************************************************************* 385 * Memory Controller's SMMU client configuration registers 386 ******************************************************************************/ 387 #define MC_SMMU_CLIENT_CONFIG1 0x44 388 #define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000 389 #define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17) 390 #define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17) 391 #define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21) 392 #define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21) 393 #define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29) 394 #define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29) 395 396 #define MC_SMMU_CLIENT_CONFIG2 0x48 397 #define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000 398 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11) 399 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11) 400 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13) 401 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13) 402 403 #define MC_SMMU_CLIENT_CONFIG3 0x4c 404 #define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0 405 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7) 406 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7) 407 408 #define MC_SMMU_CLIENT_CONFIG4 0xb9c 409 #define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0 410 #define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1) 411 #define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1) 412 #define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5) 413 #define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5) 414 #define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13) 415 #define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13) 416 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15) 417 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15) 418 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17) 419 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17) 420 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22) 421 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22) 422 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26) 423 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26) 424 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30) 425 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30) 426 427 #define MC_SMMU_CLIENT_CONFIG5 0xbac 428 #define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0 429 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0) 430 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0) 431 432 #ifndef __ASSEMBLY__ 433 434 #include <mmio.h> 435 436 static inline uint32_t tegra_mc_read_32(uint32_t off) 437 { 438 return mmio_read_32(TEGRA_MC_BASE + off); 439 } 440 441 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 442 { 443 mmio_write_32(TEGRA_MC_BASE + off, val); 444 } 445 446 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 447 { 448 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 449 } 450 451 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 452 { 453 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 454 } 455 456 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ 457 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 458 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 459 460 #define mc_set_smmu_unordered_boot_so_mss(id, client) \ 461 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 462 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 463 464 #define mc_set_tsa_passthrough(client) \ 465 { \ 466 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ 467 (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ 468 ~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 469 TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 470 } 471 472 #define mc_set_forced_coherent_cfg(client) \ 473 { \ 474 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 475 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \ 476 } 477 478 #define mc_set_forced_coherent_so_dev_cfg(client) \ 479 { \ 480 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 481 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 482 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 483 } 484 485 #define mc_set_forced_coherent_axid_so_dev_cfg(client) \ 486 { \ 487 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 488 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 489 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \ 490 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 491 } 492 493 /******************************************************************************* 494 * Handler to read memory configuration settings 495 * 496 * Implemented by SoCs under tegra/soc/txxx 497 ******************************************************************************/ 498 tegra_mc_settings_t *tegra_get_mc_settings(void); 499 500 #endif /* __ASSMEBLY__ */ 501 502 #endif /* __MEMCTRLV2_H__ */ 503