fix(cpufeat): enable access to extended BRPs/WRPs

Access to Extended Breakpoints(BRPs) and Watchpoints(WRPs) are enabled
through EBWE bit and this available from DebugV8P9. So enable access to
mode

fix(cpufeat): enable access to extended BRPs/WRPs

Access to Extended Breakpoints(BRPs) and Watchpoints(WRPs) are enabled
through EBWE bit and this available from DebugV8P9. So enable access to
mode select register default from lower EL's.

Though this bit RES0 when we have less than 16 BRPs/WRPs the Mode select
register is also RAZ/WI. So having EBWE write by default is harmless.
And will avoid trap to EL3 when enable access to bank selection when we
have more than 16 BRPs/WRPs.

Change-Id: Ib308be758c0beedde05a5558b0d24a161b79273a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpufeat): use of additional breakpoints

Extended Breakpoints access through mdcr_el3.ebwe is available
only when there are greater than 16 breakpoints implemented.
Otherwise the EBWE Bit is RES0

fix(cpufeat): use of additional breakpoints

Extended Breakpoints access through mdcr_el3.ebwe is available
only when there are greater than 16 breakpoints implemented.
Otherwise the EBWE Bit is RES0 and we could skip enabling Extended
Breakpoint access.

Ref: https://developer.arm.com/documentation/111107/2025-09/AArch64-Registers/MDCR-EL3--Monitor-Debug-Configuration-Register--EL3-?lang=en

Change-Id: I2b2147e83d65ee9b0492d3cf3adafd5c8cbe17f5
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed

feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a

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