fix(cpus): workaround for Neoverse V1 erratum 3888016

Neoverse V1 erratum 3888016 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2. It is still open.

Set CPUACTLR2_EL1 bit 22 to

fix(cpus): workaround for Neoverse V1 erratum 3888016

Neoverse V1 erratum 3888016 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2. It is still open.

Set CPUACTLR2_EL1 bit 22 to 1 so that multiple loads to the same
Non-Cacheable or Device GRE cache line are not linked to a single read
request, preventing a younger ordered load from reading stale data
brought in by an earlier load and thereby preserving the required
dependency, fetch-ordered-before, or barrier-ordered-before semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ief57b3c7e9feb123ca2783a751d95d1e148a8e41
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 1674403

Neoverse V1 erratum 1674403 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR3_EL1 bit 12 to 1 to disable res

fix(cpus): workaround for Neoverse V1 erratum 1674403

Neoverse V1 erratum 1674403 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR3_EL1 bit 12 to 1 to disable result-bus sharing in the
Floating-point/Advanced SIMD unit, which removes the
micro-architectural condition where sequences of divide or square-root
operations around a mispredicted branch can deadlock, at the cost of
less than 0.5% performance loss on SPECfp workloads.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: I9b13734c758e62daf073e321e3115c1503d9cbd1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 1654562

Neoverse V1 erratum 1654562 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR2_EL1[1] to 1 so that a store-re

fix(cpus): workaround for Neoverse V1 erratum 1654562

Neoverse V1 erratum 1654562 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR2_EL1[1] to 1 so that a store-release instruction is
not dispatched before it becomes the oldest store in the queue,
preventing the micro-architectural condition where a streaming store
followed by a retried store-release and a later cacheable
non-streaming store can corrupt data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ic56420b855ed7cd527cfb7afef0237815439e08e
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 1619807

Neoverse V1 erratum 1619807 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR_EL1 bit 11 to 1 so that all con

fix(cpus): workaround for Neoverse V1 erratum 1619807

Neoverse V1 erratum 1619807 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR_EL1 bit 11 to 1 so that all context synchronization
events flush the L0 Macro-op cache, ensuring that when software step
or halt step is enabled the core takes the exception after the
intended single instruction rather than after multiple instructions
from the L0 Macro-op cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ie9595ccbcba04892ebfbfffc067bc2fe1b5a1e6e
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 1618636

Neoverse V1 erratum 1618636 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR5_EL1 bit 8 to 1 to avoid the de

fix(cpus): workaround for Neoverse V1 erratum 1618636

Neoverse V1 erratum 1618636 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Set CPUACTLR5_EL1 bit 8 to 1 to avoid the deadlock that can occur when
an AArch32 conditional Floating Point or Advanced SIMD instruction on
the correct path follows a flushed FP/Advanced SIMD instruction after
a mispredicted branch, accepting a small increase in core power
consumption.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Id2c0079f84e1469e7e52b1cdb8690c88c5f3ebb3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 1618634

Neoverse V1 erratum 1618634 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Before enabling the MMU, set CPUACTLR_EL1 bi

fix(cpus): workaround for Neoverse V1 erratum 1618634

Neoverse V1 erratum 1618634 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Before enabling the MMU, set CPUACTLR_EL1 bit 13 to 1 to disable the
performance feature that can cause incorrect instruction execution
when a table-walk response arrives to the L1 instruction TLB at the
same time as a lookup overlapping the incoming mapping.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ie02aae1382f4897eb4d78c0e86b67fca3a2fcb47
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse V1 erratum 1542436

Neoverse V1 erratum 1542436 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Enable the architectural workaround by setti

fix(cpus): workaround for Neoverse V1 erratum 1542436

Neoverse V1 erratum 1542436 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

Enable the architectural workaround by setting CPUACTLR4_EL1 bit 14 to
1 during boot so that SVE MOVPRFX-prefixed integer multiply
instructions cannot corrupt their scalable vector destination
register, accepting a slight performance impact on SVE prefixing with
MOVPRFX.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401781/latest

Change-Id: Ia386b8d4fc7ec8491cc8b68fce4027d4f3c6b843
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): unconstrain WORKAROUND_CVE_2025_0647

Conditional flag enables are strongly discouraged in TF-A because they
cause cyclic dependencies that we are not equipped to deal with. On a
real plat

fix(cpus): unconstrain WORKAROUND_CVE_2025_0647

Conditional flag enables are strongly discouraged in TF-A because they
cause cyclic dependencies that we are not equipped to deal with. On a
real platform, ARM_ARCH_{MAJOR, MINOR} should be set in platform.mk but
WORKAROUND_CVE_2025_0647 gets its value before platform.mk is evaluated.

Further, WORKAROUND_CVE_2025_0647 is only present on cores the feature
set of which is known ahead of time. Using ARM_ARCH_{MAJOR, MINOR} is
redundant and incorrect (as it sidesteps the feature detection
mechanism).

This patch solves both of these issues by making
WORKAROUND_CVE_2025_0647 unconstrained by ARM_ARCH_{MAJOR, MINOR} and
making it buildable on a v8.0 target. Running the workaround will only
happen on affected cores which, by definition, all implement armv8.5 so
doing any checks in unnecessary.

Change-Id: Ia164077f09b552d42b558ada4f6036cabbd34f64
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): use correct workaround for erratum N1 3324349

The Neoverse N1 does not have FEAT_SB and the workaround writeup
reflects this - it calls for an isb, unlike similar errata on cores that
hav

fix(cpus): use correct workaround for erratum N1 3324349

The Neoverse N1 does not have FEAT_SB and the workaround writeup
reflects this - it calls for an isb, unlike similar errata on cores that
have FEAT_SB. This patch updates the barrier to the right one for this
core.

This was caught by accidentally setting ENABLE_FEAT_SB=1 on fvp which
predictably blew up. Up to now, this has been tested with
ENABLE_FEAT_SB=2 which would have silently skipped the workaround.

Change-Id: I14c881b67b821f11bac5217dbf9e6ceee5dbe783
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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fix(cpus): only turn off CME when it is present

Patch 93c7e7019 made the old ERRATA_SME_POWER_DOWN specific to each CPU.
However it failed to account for the fact that some CPUs have SME
support con

fix(cpus): only turn off CME when it is present

Patch 93c7e7019 made the old ERRATA_SME_POWER_DOWN specific to each CPU.
However it failed to account for the fact that some CPUs have SME
support configurable and unconditionally access the SVCR register. When
support isn't included, the lack of FEAT_SME will cause a trap. So add a
check to support both configurations.

Change-Id: Ic21bff5d51109ec6b3117f85f6d37f052076f49a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "bk/wa_fixes" into integration

* changes:
docs(cpus): explain why the ARCH_WORKAROUND_3 pseudo-erratum is needed
fix(cpus): return ERRATA_MISSING when errata not found

Merge changes from topic "bk/wa_fixes" into integration

* changes:
docs(cpus): explain why the ARCH_WORKAROUND_3 pseudo-erratum is needed
fix(cpus): return ERRATA_MISSING when errata not found
style(smccc): group the ARCH_WORKAROUND_Xs together
style(cpus): add spaces around the CVE-2022-23960 on Neoverse V2
refactor(cpus): clean up FEAT_CSV2 checkers

show more ...

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch m

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(security): avoid CVE_2025_0647 for bl2 build

If a platform defines the flag RESET_TO_BL2, BL2 will include the CPU
library files. If the CPU is Armv8.5 or higher, the workaround flag
WORKAROUND_

fix(security): avoid CVE_2025_0647 for bl2 build

If a platform defines the flag RESET_TO_BL2, BL2 will include the CPU
library files. If the CPU is Armv8.5 or higher, the workaround flag
WORKAROUND_CVE_2025_0647 will be enable. And then there are compilation
issues, as some symbols from wa_cve_2025_0647_cpprctx.S are not found.
This has been seen on lts-v2.12 branch when preparing lts-v2.12.11 tag.
The platform RD1AE failed to compiled.

To fix this issue add the workaround only for BL31 image build, this is
similar to `override_vector_table` already done in parts of cpu lib.

Change-Id: Icdf63de6ed8413761561406eceaeddd69118b144
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): return ERRATA_MISSING when errata not found

There are 2 cases in which an erratum will not be found in the list:
a) there is no workaround implemented
b) there is a workaround implemented

fix(cpus): return ERRATA_MISSING when errata not found

There are 2 cases in which an erratum will not be found in the list:
a) there is no workaround implemented
b) there is a workaround implemented but it has not been compiled in

Neither case implies that the erratum does not apply - for option a) it
could mean that the erratum is newer than TF-A's awareness and in option
b) it could mean that the flag was forgotten to be set.

Unfortunately, this can't be done in isolation and must be accompanied
by untangling the complicated relationship between CVE identifiers and
the return codes to ensure everything remains the same. First, make
the CVE_2017_5715 and CVE_2022_23960 relationship in the WA_3 SMC call
explicit instead of relying on the checker functions. Then, add semantic
defines for the return values of the workarounds as 0, 1, and -1 are
ambiguous and confusing. This allows the application of a consistent
return pattern.

Change-Id: Ibfae2cd06212dc59b4730a6dca6e9aee1f341609
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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style(cpus): add spaces around the CVE-2022-23960 on Neoverse V2

Makes grepping easier.

Change-Id: Iaadbc4ce16f04590189bfc3868008b55b37764dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

refactor(cpus): clean up FEAT_CSV2 checkers

The cortex A72, A73, and A75 have a major revision (r1p0, r1p0, r3p0
respectively) where they implement FEAT_CSV to mitigate against
CVE-2017-5715. Replac

refactor(cpus): clean up FEAT_CSV2 checkers

The cortex A72, A73, and A75 have a major revision (r1p0, r1p0, r3p0
respectively) where they implement FEAT_CSV to mitigate against
CVE-2017-5715. Replace the complicated checkers around the feature with
standard revision checks based on the revision where FEAT_CSV was
introduced. This simplifies code and aligns with the revision based
recommendation on whether mitigations should be implemented in [0].

[0]: https://developer.arm.com/documentation/110280/latest/

Change-Id: If848952d15f5553cc385bb37e5f08f6e5b85fcd8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): use hint instruction instead of the psb mnemonic

Sometimes the file will be compiled without the compiler having
knowledge of the psb instruction. Use the hint synonym to improve
compatib

fix(cpus): use hint instruction instead of the psb mnemonic

Sometimes the file will be compiled without the compiler having
knowledge of the psb instruction. Use the hint synonym to improve
compatibility.

Change-Id: Ibb344223fea1c0c0e97e87e2d509b215cd608cc7
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cpus): correct comments for Cortex-A720 erratum 3711910" into integration

fix(cpus): correct comments for Cortex-A720 erratum 3711910

Correct the comments for Cortex-A720 erratum 3711910 in cpu-ops.mk

Change-Id: I8b070927c19c5982b2ded815e7673e0c4ff11b5f
Signed-off-by: Xi

fix(cpus): correct comments for Cortex-A720 erratum 3711910

Correct the comments for Cortex-A720 erratum 3711910 in cpu-ops.mk

Change-Id: I8b070927c19c5982b2ded815e7673e0c4ff11b5f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): reorder docs for Cortex-A76 erratum 1165522

The documentation for Cortex-A76 erratum 1165522 is not in
ascending order. Reorder it to comply with the convention.

SDEN documentation:
http

fix(cpus): reorder docs for Cortex-A76 erratum 1165522

The documentation for Cortex-A76 erratum 1165522 is not in
ascending order. Reorder it to comply with the convention.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: I2e7c05d6355dfbaa69170fc098adc1f12edc6658
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): update revisions for Cortex-A76 erratum 1946160

Cortex-A76 erratum 1946160 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1.
It is still open.

Ne

fix(cpus): update revisions for Cortex-A76 erratum 1946160

Cortex-A76 erratum 1946160 is a Cat B erratum that applies
to revisions r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1.
It is still open.

New revisions are found being affected by erratum 1946160.
Update accordingly.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: I532ce10c3037dd77e31d7df849beb578f8b5e7b4
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76 erratum 1207823

Cortex-A76 erratum 1207823 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

The exclusive monitor might

fix(cpus): workaround for Cortex-A76 erratum 1207823

Cortex-A76 erratum 1207823 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

The exclusive monitor might end up tracking an incorrect cache
line in the presence of a VA-alias, causing a false pass on
the exclusive access sequence. This erratum can be avoided by
setting CPUACTLR2_EL1[11] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: Ife06401f3946884872b733f98c08e61f586d8353
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76 erratum 1165347

Cortex-A76 erratum 1165347 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

This erratum can lead to liv

fix(cpus): workaround for Cortex-A76 erratum 1165347

Cortex-A76 erratum 1165347 is a Cat B erratum that applies
to revisions r0p0, r1p0, and r2p0, and is fixed in r3p0.

This erratum can lead to livelock under certain condition, which
can be avoided by by setting CPUACTLR2_EL1[0] to 1 and CPUACTLR2_EL1[15]
to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-885749/latest

Change-Id: If9817dc26d0df835d749f506de63a4f613735723
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(cpus): workaround for Cortex-A65AE erratum 1638571" into integration