fix(cpus): workaround for Cortex-A77 erratum 3888015

Cortex-A77 erratum 3888015 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1. It is still open.

The erratum can be avoided by settin

fix(cpus): workaround for Cortex-A77 erratum 3888015

Cortex-A77 erratum 3888015 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1. It is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1, which
disables linking multiple Non-Cacheable or Device GRE loads to the
same cache-line read request and prevents younger loads from reading
stale data at the cost of reduced Non-Cacheable and Device GRE read
bandwidth.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I0a356e05dff3dce9b9ba8c924556ebdfae391f67
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): update Cortex-A77 applied revision for CVE-2024-5660

The Cortex-A77 erratum 3439000 is duplication of CVE-2024-5660
it is a Cat B erratum that applies to revisions r0p0, r1p0, r1p1.
It is

fix(cpus): update Cortex-A77 applied revision for CVE-2024-5660

The Cortex-A77 erratum 3439000 is duplication of CVE-2024-5660
it is a Cat B erratum that applies to revisions r0p0, r1p0, r1p1.
It is still open. Therefore Change the applied CPU revisions since
this erratum is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: Ic28075796a928301cc5ebb48ccb6019594801e2a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A77 erratum 1515815

Cortex-A77 erratum 1515815 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.

Set CPUACTLR_EL1[11] to 1 so that the L

fix(cpus): workaround for Cortex-A77 erratum 1515815

Cortex-A77 erratum 1515815 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.

Set CPUACTLR_EL1[11] to 1 so that the L0 Macro-op cache is flushed for
all context synchronization events, ensuring that only a single
instruction is executed before a software step or halt step exception
is taken.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I1e6faf5a699734f9a5be848807e9c3fa5110d569
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A77 erratum 1273521

Cortex-A77 erratum 1273521 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Cortex-A77 erratum 1273521

Cortex-A77 erratum 1273521 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1 to
increase the mispredict-to-fetch latency, which will have some impact
on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I34677057ba74721a35bdb34488b5a500397b0e88
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A77 erratum 1253791

Cortex-A77 erratum 1253791 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTL

fix(cpus): workaround for Cortex-A77 erratum 1253791

Cortex-A77 erratum 1253791 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR3_EL1[10] to 1, which
prevents parallel execution of divide and square root instructions.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: I76895d167a477246ff5bc6c87237fb4f9724c547
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A77 erratum 1220737

Cortex-A77 erratum 1220737 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUECTL

fix(cpus): workaround for Cortex-A77 erratum 1220737

Cortex-A77 erratum 1220737 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUECTLR_EL1[25:24] to 0b11,
which disables write streaming to the L2. This will have an impact on
performance for streaming workloads.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: Iad21fad2b774234b1df808a4074eb3aabc01f2f3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A77 erratum 1204882

Cortex-A77 erratum 1204882 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided if software sets C

fix(cpus): workaround for Cortex-A77 erratum 1204882

Cortex-A77 erratum 1204882 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

This erratum can be avoided if software sets CPUACTLR2_EL1[11] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: Id1ffbff103644966e657eff8a7cd5ab83532816d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A77 erratum 1160841

Cortex-A77 erratum 1160841 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

The workaround is to set CPUACTLR2_EL1[0] to 1

fix(cpus): workaround for Cortex-A77 erratum 1160841

Cortex-A77 erratum 1160841 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.

The workaround is to set CPUACTLR2_EL1[0] to 1 and CPUACTLR2_EL1[15]
to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest

Change-Id: Iae33d55501ebd9bd0770e5543a42efbda58af701
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 4302973

Cortex-A78AE erratum 4302973 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3. It is still open.

This erratum can be avoide

fix(cpus): workaround for Cortex-A78AE erratum 4302973

Cortex-A78AE erratum 4302973 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3. It is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: I54a5e04c44e4dad33287c795760135c87f4fd193
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 3888018

Cortex-A78AE erratum 3888018 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3. It is still open.

The erratum can be avoided

fix(cpus): workaround for Cortex-A78AE erratum 3888018

Cortex-A78AE erratum 3888018 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3. It is still open.

The erratum can be avoided by setting CPUACTLR2_EL1[22] to 1, which
disables linking multiple Non-Cacheable or Device GRE loads to the
same read request for a cache line.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: Idba664c1e2b8bdc031dc24bc57aa5366be8f1e8e
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 2779481

Cortex-A78AE erratum 2779481 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.

The erratum can be avoided by

fix(cpus): workaround for Cortex-A78AE erratum 2779481

Cortex-A78AE erratum 2779481 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.

The erratum can be avoided by setting CPUACTLR3_EL1[47].

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: If45cd8efe24768aaa0d31f56b3b297ba1c10980f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 2743229

Cortex-A78AE erratum 2743229 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.

This erratum can be avoided b

fix(cpus): workaround for Cortex-A78AE erratum 2743229

Cortex-A78AE erratum 2743229 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.

This erratum can be avoided by setting CPUACTLR5_EL1[56:55] to 0b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: Ic9a60a695eb00574c25490376337a4ad09b9b2c7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 2466780

Cortex-A78AE erratum 2466780 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

This erratum can be avoided by flus

fix(cpus): workaround for Cortex-A78AE erratum 2466780

Cortex-A78AE erratum 2466780 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2.

This erratum can be avoided by flushing the mop cache following a
write to SCR_EL3, HCR_EL2, or SCTLR_ELx. This is implemented by an EL3
sequence that programs implementation-defined CPUPSELR_EL3,
CPUPOR_EL3, CPUPMR_EL3, and CPUPCR_EL3 via S3_6_c15_c8_x writes
followed by an ISB, executed as soon as possible after boot.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: I724c4bc81ff0ba06576410251bc7895a3bb00251
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 2242639

Cortex-A78AE erratum 2242639 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2. There is no workaround
for revision

fix(cpus): workaround for Cortex-A78AE erratum 2242639

Cortex-A78AE erratum 2242639 is a Cat B erratum that applies to
revisions r0p0, r0p1. It is fixed in r0p2. There is no workaround
for revision r0p0, contact Arm for details.

This erratum can be avoided by applying an EL3 patch that programs
implementation-defined CPUPSELR_EL3, CPUPOR_EL3, CPUPMR_EL3, and
CPUPCR_EL3 registers via a sequence of S3_6_c15_c8_x writes followed
by an ISB, applied early in the boot sequence before any of the
possible errata conditions are met.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: I3f58b1a4defeee64b9e5d8c1a3f96eeca9f9f412
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 1827433

Cortex-A78AE erratum 1827433 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

Set CPUACTLR2_EL1[2] to force Atomic Store

fix(cpus): workaround for Cortex-A78AE erratum 1827433

Cortex-A78AE erratum 1827433 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

Set CPUACTLR2_EL1[2] to force Atomic Store operations to write-back
memory to be performed in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: Iaa980074ad5d39b9ca229c7e2d41c6092b93eea9
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A78AE erratum 1827431

Cortex-A78AE erratum 1827431 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A78AE erratum 1827431

Cortex-A78AE erratum 1827431 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.

This erratum can be avoided by setting CPUECTLR_EL1[53] to 1, which
disables the allocation of splintered pages in the L2 TLB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest

Change-Id: I05158d1dfcc4b70f4a96656c26f040aba9e74d70
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge changes from topic "xl/cortex_a710-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A710 erratum 4302969
fix(cpus): workaround for Cortex-A710 erratum 3888122
fix(cpu

Merge changes from topic "xl/cortex_a710-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A710 erratum 4302969
fix(cpus): workaround for Cortex-A710 erratum 3888122
fix(cpus): workaround for Cortex-A710 erratum 1887102
fix(cpus): workaround for Cortex-A710 erratum 1847092
fix(cpus): workaround for Cortex-A710 erratum 1793423
fix(cpus): workaround for Cortex-A710 erratum 1785648

show more ...

fix(cpus): workaround for Cortex-A710 erratum 4302969

Cortex-A710 erratum 4302969 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r2p1. It is still open.

Set CPUACTLR5_EL1[50] to 1 s

fix(cpus): workaround for Cortex-A710 erratum 4302969

Cortex-A710 erratum 4302969 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r2p1. It is still open.

Set CPUACTLR5_EL1[50] to 1 so that TLBI instructions preserve the
upper ASID bits even when TCR_ELx.AS is 0.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I24036ec15ccb6e703aa16aacdbe9f15a775bfc55
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A710 erratum 3888122

Cortex-A710 erratum 3888122 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r2p1. It is still open.

Set CPUACTLR2_EL1[22] to 1 t

fix(cpus): workaround for Cortex-A710 erratum 3888122

Cortex-A710 erratum 3888122 is a Cat B erratum that applies to
revisions r0p0, r1p0, r2p0, r2p1. It is still open.

Set CPUACTLR2_EL1[22] to 1 to disable linking multiple Non-Cacheable
or Device GRE loads to the same cache-line read request, preventing
younger loads from reading stale data at the cost of reduced
Non-cacheable and Device GRE read bandwidth in streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: Icac55672ab9193422ab7a963555fb5fb2b5db59f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A710 erratum 1887102

Cortex-A710 erratum 1887102 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r2p0.

To avoid this erratum, software shoul

fix(cpus): workaround for Cortex-A710 erratum 1887102

Cortex-A710 erratum 1887102 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r2p0.

To avoid this erratum, software should either set CPUACTLR2_EL1[27] to
1 to allow the injected DSB to invalidate translation table entries
caching translations for TRBE, or execute an Inner Shareable TLBI by
VA or TLBI by VMID before the DSB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I9a98074af3147639b3b4b910cf2ee1b3638b65d5
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A710 erratum 1847092

Cortex-A710 erratum 1847092 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Cortex-A710 erratum 1847092

Cortex-A710 erratum 1847092 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR5_EL1[10] to 1. Setting
CPUACTLR5_EL1[10] to 1 will impact performance on AArch64 code.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: Ibc516251b4e3deed27d14ba63ea58f6612b46590
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge changes from topic "xl/n1-errata" into integration

* changes:
fix(cpus): workaround for Neoverse N1 erratum 925373
fix(cpus): workaround for Neoverse N1 erratum 3888013
fix(cpus): workar

Merge changes from topic "xl/n1-errata" into integration

* changes:
fix(cpus): workaround for Neoverse N1 erratum 925373
fix(cpus): workaround for Neoverse N1 erratum 3888013
fix(cpus): workaround for Neoverse N1 erratum 1791580

show more ...

Merge "fix(cpus): workaround for Cortex-A76AE erratum 3888014" into integration

Merge "fix(cpus): workaround for Cortex-A715 erratum 2285473" into integration

Merge changes from topic "xl/cortex_a715-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 2238661
fix(cpus): workaround for Cortex-A715 erratum 2275754
fix(cpu

Merge changes from topic "xl/cortex_a715-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 2238661
fix(cpus): workaround for Cortex-A715 erratum 2275754
fix(cpus): workaround for Cortex-A715 erratum 2284544
fix(cpus): workaround for Cortex-A715 erratum 2239006
fix(cpus): workaround for Cortex-A715 erratum 2292761

show more ...