1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_a715_3699560 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31cpu_reset_prologue cortex_a715 32 33workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 34 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 35workaround_reset_end cortex_a715, ERRATUM(2331818) 36 37check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) 38 39workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187 40 /* GCR_EL1 is only present with FEAT_MTE2. */ 41 mrs x1, ID_AA64PFR1_EL1 42 ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 43 cmp x0, #MTE_IMPLEMENTED_ELX 44 bne #1f 45 sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT 46 471: 48 /* Mitigation upon ERETAA and ERETAB. */ 49 mov x0, #2 50 msr CORTEX_A715_CPUPSELR_EL3, x0 51 isb 52 ldr x0, =0xd69f0bff 53 msr CORTEX_A715_CPUPOR_EL3, x0 54 ldr x0, =0xfffffbff 55 msr CORTEX_A715_CPUPMR_EL3, x0 56 mov x1, #0 57 orr x1, x1, #(1<<0) 58 orr x1, x1, #(3<<4) 59 orr x1, x1, #(0xf<<6) 60 orr x1, x1, #(1<<13) 61 orr x1, x1, #(1<<53) 62 msr CORTEX_A715_CPUPCR_EL3, x1 63workaround_reset_end cortex_a715, ERRATUM(2344187) 64 65check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0) 66 67workaround_reset_start cortex_a715, ERRATUM(2376701), ERRATA_A715_2376701 68sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(0) 69workaround_reset_end cortex_a715, ERRATUM(2376701) 70 71check_erratum_ls cortex_a715, ERRATUM(2376701), CPU_REV(1, 0) 72 73workaround_reset_start cortex_a715, ERRATUM(2409570), ERRATA_A715_2409570 74sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(32) 75workaround_reset_end cortex_a715, ERRATUM(2409570) 76 77check_erratum_range cortex_a715, ERRATUM(2409570), CPU_REV(1, 0), CPU_REV(1, 0) 78 79workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290 80/* Erratum 2413290 workaround is required only if SPE is enabled */ 81#if ENABLE_SPE_FOR_NS != 0 82 /* Check if Static profiling extension is implemented or present. */ 83 mrs x1, id_aa64dfr0_el1 84 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 85 cbz x0, 1f 86 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 87 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57) 88 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58) 891: 90#endif 91workaround_reset_end cortex_a715, ERRATUM(2413290) 92 93check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0) 94 95workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 96 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) 97workaround_reset_end cortex_a715, ERRATUM(2420947) 98 99check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) 100 101workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 102 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 103workaround_reset_end cortex_a715, ERRATUM(2429384) 104 105check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 106 107workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 108 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 109workaround_reset_end cortex_a715, ERRATUM(2561034) 110 111check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 112 113workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106 114 mov x0, #3 115 msr CORTEX_A715_CPUPSELR_EL3, x0 116 isb 117 ldr x0, =0xd503339f 118 msr CORTEX_A715_CPUPOR_EL3, x0 119 ldr x0, =0xfffff3ff 120 msr CORTEX_A715_CPUPMR_EL3, x0 121 mov x0, #1 122 orr x0, x0, #(3<<4) 123 orr x0, x0, #(0xf<<6) 124 orr x0, x0, #(1<<13) 125 orr x0, x0, #(1<<20) 126 orr x0, x0, #(1<<22) 127 orr x0, x0, #(1<<31) 128 orr x0, x0, #(1<<50) 129 msr CORTEX_A715_CPUPCR_EL3, x0 130workaround_reset_end cortex_a715, ERRATUM(2728106) 131 132check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1) 133 134workaround_reset_start cortex_a715, ERRATUM(2804830), ERRATA_A715_2804830 135 /* Workaround changes based on CORE_CACHE_PROTECTIONS field (bit 1) */ 136 mrs x0, CORTEX_A715_CPUCFR_EL1 137 tbz x0, #1, wa_2804830_core_cache_prot_false 138 139 /* CORE_CACHE_PROTECTIONS==true */ 140 sysreg_bit_set CORTEX_A715_CPUACTLR3_EL1, BIT(2) 141 sysreg_bit_set CORTEX_A715_CPUECTLR_EL1, BIT(23) 142 b wa_2804830_done 143 144 /* CORE_CACHE_PROTECTIONS==false */ 145wa_2804830_core_cache_prot_false: 146 sysreg_bit_set CORTEX_A715_CPUECTLR2_EL1, BIT(7) 147 148wa_2804830_done: 149workaround_reset_end cortex_a715, ERRATUM(2804830) 150 151check_erratum_ls cortex_a715, ERRATUM(2804830), CPU_REV(1, 2) 152 153add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560 154 155check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3) 156 157workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 158#if IMAGE_BL31 159 /* 160 * The Cortex-A715 generic vectors are overridden to apply errata 161 * mitigation on exception entry from lower ELs. 162 */ 163 override_vector_table wa_cve_vbar_cortex_a715 164#endif /* IMAGE_BL31 */ 165workaround_reset_end cortex_a715, CVE(2022, 23960) 166 167check_erratum_ls cortex_a715, CVE(2022, 23960), CPU_REV(1, 0) 168 169cpu_reset_func_start cortex_a715 170 /* Disable speculative loads */ 171 msr SSBS, xzr 172 enable_mpmm 173cpu_reset_func_end cortex_a715 174 175 /* ---------------------------------------------------- 176 * HW will do the cache maintenance while powering down 177 * ---------------------------------------------------- 178 */ 179func cortex_a715_core_pwr_dwn 180 /* --------------------------------------------------- 181 * Enable CPU power down bit in power control register 182 * --------------------------------------------------- 183 */ 184 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 185 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 186 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 187 isb 188 ret 189endfunc cortex_a715_core_pwr_dwn 190 191 /* --------------------------------------------- 192 * This function provides Cortex-A715 specific 193 * register information for crash reporting. 194 * It needs to return with x6 pointing to 195 * a list of register names in ascii and 196 * x8 - x15 having values of registers to be 197 * reported. 198 * --------------------------------------------- 199 */ 200.section .rodata.cortex_a715_regs, "aS" 201cortex_a715_regs: /* The ascii list of register names to be reported */ 202 .asciz "cpuectlr_el1", "" 203 204func cortex_a715_cpu_reg_dump 205 adr x6, cortex_a715_regs 206 mrs x8, CORTEX_A715_CPUECTLR_EL1 207 ret 208endfunc cortex_a715_cpu_reg_dump 209 210declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 211 cortex_a715_reset_func, \ 212 cortex_a715_core_pwr_dwn 213