feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to m

feat(gicv5): initialise the IRS

Do IRS initialisation that's only accessible from the EL3 interrupt
domain. Relies on the platform to provide SPI domain assignments and
trigger modes as well as to map the config frame in device nGnRnE
memory. All wires will default to NS and the platform may override this.

Change-Id: Icbd43503753cd76fd3d80ed47eba6926494bc323
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux t

feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux to fully boot.
This is expected to be fully replaced with context management when
adding world switching support as some of these are expected to be
shared between worlds.

Change-Id: I59a7b5a63f878c9a717ef81e977be7133a402f3f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(locks): add non-blocking spinlock_try() API

Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on succes

feat(locks): add non-blocking spinlock_try() API

Add a non-blocking `spin_trylock()` function to the existing spinlock
implementation. This API attempts to acquire the lock and returns `1`
on success or `0` if the lock is already held. It enables conditional
locking scenarios where blocking is undesirable.

Change-Id: I9483206952d1a34dc245ebf69e80c3645b658946
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the nec

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.

Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.

Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support fo

feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support for the latest Armv9 features. As such it is entirely backwards
incompatible with GICv3/v4.

This patch adds the necessary boilerplate to select a build with GICv5.
The GIC has always had two parts. BL31 deals directly with the CPU
interface while platform code is responsible for managing the IRI. In v5
this split is formalised and the CPU interface, FEAT_GCIE, may be
implemented on its own. So reflect this split in our code with
ENABLE_FEAT_GCIE which only affects BL31 and the GICv5 IRI lies in the
generic GIC driver.

No actual functionality yet.

Change-Id: I97a0c3ba708877c213e50e7ef148e3412aa2af90
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(psci): add API to get number of CPUs currently in ON state" into integration

Merge changes from topic "mb/misc-drtm-fixes" into integration

* changes:
fix(drtm): measure and record the DLME EP offset instead of absolute address
fix(drtm): set correct max region mask for

Merge changes from topic "mb/misc-drtm-fixes" into integration

* changes:
fix(drtm): measure and record the DLME EP offset instead of absolute address
fix(drtm): set correct max region mask for DMA protection to 0xFFFF
fix(drtm): correct PROTECT_MEM_REGION value as per DRTM specification
fix(drtm): add event name data for separator event entries

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feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum

feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum is fixed in certain implementations of r2p0 which can be
determined by reading the IMP_CLUSTERREVIDR_EL1[1] register field
where a set bit indicates that the erratum is fixed in this part.

The workaround is to set the CLUSTERACTLR_EL1 bits [21:20] to 0x3
which ignores CBusy from the system interconnect and
setting CLUSTERACTLR_EL1 bit [8] to 1 to assert CBusy from DSU to
all the cores when DSU is busy.

SDEN: https://developer.arm.com/documentation/SDEN-2453103/1200/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I87aa440ab5c35121aff703032f5cf7a62d0b0bb4

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feat(psci): add API to get number of CPUs currently in ON state

Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state

feat(psci): add API to get number of CPUs currently in ON state

Introduce a new PSCI helper function `psci_num_cpus_running_on_safe()`
to return the number of CPUs that are currently in the ON state.
This API locks the PSCI power state data to ensure consistency and
is safe to call in concurrent environments.

This utility can assist components that need to reason about system
CPU activity or coordinate operations based on active CPUs.

Change-Id: Ie15aa4bd393a5f01e7cd80ae8a9b28707fde7c53
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(libc): add the memcpy declaration back

Patch 34d7f196b moved definitions to a new file but missed that of
memcpy. Put it back.

Change-Id: I5e9797e611e6f1f97232f03de98f81db86a66c2a
Signed-off-by

fix(libc): add the memcpy declaration back

Patch 34d7f196b moved definitions to a new file but missed that of
memcpy. Put it back.

Change-Id: I5e9797e611e6f1f97232f03de98f81db86a66c2a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15].

fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I703f0e6ee122e44a9bc284d90f1465039e3b40e4
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(errata): keep leading zeros in CVE ID prints" into integration

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

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Merge "feat(cpus): update cpu_check_csv2 check" into integration

Merge "fix(xlat): change MT_DEVICE to map to nGnRnE" into integration

feat(cpus): update cpu_check_csv2 check

Update the cpu_check_csv2 logic to allow ID_AA64PFR0_EL1.CSV2
values up to 3. With the introduction of FEAT_CSV2_3,
the architectural limit for CSV2 has been

feat(cpus): update cpu_check_csv2 check

Update the cpu_check_csv2 logic to allow ID_AA64PFR0_EL1.CSV2
values up to 3. With the introduction of FEAT_CSV2_3,
the architectural limit for CSV2 has been extended,
making values from 0 to 3 valid.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8473047ed4ad759b7b506161a76774ac21555d31

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Merge changes from topic "st_fixes" into integration

* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3

Merge changes from topic "st_fixes" into integration

* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3
fix(st-bsec): rename OTPSR field
fix(st-crypto): do not set IPRST if BUSY flag is present
fix(st-ddr): bad refresh update level toggle sequence
fix(st-ddr): remove TODO in STM32MP2 driver
fix(stm32mp2): correct typo in definition header

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feat(stm32mp21): add RCC registers file

Add stm32mp21_rcc.h file which describes RCC peripheral registers
for STM32MP21.

Change-Id: Idd01179da3925aa4d7b4f934ebd3d95fc0780f6d
Signed-off-by: Yann Gau

feat(stm32mp21): add RCC registers file

Add stm32mp21_rcc.h file which describes RCC peripheral registers
for STM32MP21.

Change-Id: Idd01179da3925aa4d7b4f934ebd3d95fc0780f6d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(stm32mp21): add clock and reset bindings

Add device tree bindings files for STM32MP21 clocks and resets

Change-Id: I5c5576161a164a49a3c8b13baa66a371a5d2863b
Signed-off-by: Yann Gautier <yann.g

feat(stm32mp21): add clock and reset bindings

Add device tree bindings files for STM32MP21 clocks and resets

Change-Id: I5c5576161a164a49a3c8b13baa66a371a5d2863b
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(stm32mp25): add RCC register to display all IWDG flags

Add a new define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF to check all IWDG flags.

Change-Id: Id48671ae935e3100d4c42bc341d770f702d661de
Signed-off

feat(stm32mp25): add RCC register to display all IWDG flags

Add a new define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF to check all IWDG flags.

Change-Id: Id48671ae935e3100d4c42bc341d770f702d661de
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(stm32mp21): add PWR registers file

Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.

Change

feat(stm32mp21): add PWR registers file

Use the new file stm32mp21_pwr.h for STM32MP21 PWR peripheral registers
definition. Update platform code for backup domain write protection
disabling.

Change-Id: Iedfa764529bcd5119be8e94da7f7b84699e86086
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1

feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1 SoCs.

This will avoid to forget to modify all these files when a new SoC is
introduced.

Change-Id: Ib984b22a19e08af5bc1b62fe2032f10240ec9122
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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fix(drtm): set correct max region mask for DMA protection to 0xFFFF

Update `ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK` from `0xF` to
`0xFFFF` to correctly reflect the maximum number of supported D

fix(drtm): set correct max region mask for DMA protection to 0xFFFF

Update `ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK` from `0xF` to
`0xFFFF` to correctly reflect the maximum number of supported DMA
protection regions, as per the expected DRTM capability encoding.

The previous 4-bit mask limited the range to 16 regions, which is
insufficient and incorrect based on the spec's intention. This fix
extends the bitmask to 16 bits, allowing up to 65,535 regions if
supported in future implementations.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2531706f4b75125b510413870dfd4b1804e5adb6

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Merge "feat(smcc): introduce a new vendor_el3 service for ACS SMC handler" into integration

fix(xlat): change MT_DEVICE to map to nGnRnE

Previously, MT_DEVICE memory was mapped to nGnRE instead of nGnRnE. This
could cause issues if a platform with USE_COHERENT_MEM=1 mapped the
coherent mem

fix(xlat): change MT_DEVICE to map to nGnRnE

Previously, MT_DEVICE memory was mapped to nGnRE instead of nGnRnE. This
could cause issues if a platform with USE_COHERENT_MEM=1 mapped the
coherent memory region as MT_DEVICE. A core with stage 1 translation
enabled would access the region with the attributes nGnRE and a core
with stage 1 disabled would access the region with attributes nGnRnE.

This would result in accesses to a memory location with mismatched
memory attributes.

This commit changes MT_DEVICE to nGnRnE. This shouldn't introduce any
issues as nGnRnE has stronger ordering requirements.

Change-Id: Idf2e0bbea3ddb5e469a72a41f5fdb71c030d54b8
Signed-off-by: Andrei Stefanescu <andrei.stefanescu@nxp.com>

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