fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57

This patch applies CVE-2022-23960 workarounds for Cortex-A75,
Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements
the new

fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57

This patch applies CVE-2022-23960 workarounds for Cortex-A75,
Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements
the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery
hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to
enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3
is implemented for A57/A72 because some revisions are affected by both
CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace
SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details
of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c

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fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72

Implements mitigation for Cortex-A72 CPU versions that support
the CSV2 feature(from r1p0). It also applies the mitigation for

fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72

Implements mitigation for Cortex-A72 CPU versions that support
the CSV2 feature(from r1p0). It also applies the mitigation for
Cortex-A57 CPU.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I7cfcf06537710f144f6e849992612033ddd79d33

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feat(fconf): add NS load address in configuration DTB nodes

Retrieved the NS load address of configs from FW_CONFIG device tree,
and modified the prototype of "set_config_info" to update device tree

feat(fconf): add NS load address in configuration DTB nodes

Retrieved the NS load address of configs from FW_CONFIG device tree,
and modified the prototype of "set_config_info" to update device tree
information with the retrieved address.

Change-Id: Ic5a98ba65bc7aa0395c70c7d450253ff8d84d02c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "spectre_bhb" into integration

* changes:
fix(security): loop workaround for CVE-2022-23960 for Cortex-A76
refactor(el3-runtime): change Cortex-A76 implementation of CVE

Merge changes from topic "spectre_bhb" into integration

* changes:
fix(security): loop workaround for CVE-2022-23960 for Cortex-A76
refactor(el3-runtime): change Cortex-A76 implementation of CVE-2018-3639

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Merge "fix(security): workaround for CVE-2022-23960" into integration

fix(security): loop workaround for CVE-2022-23960 for Cortex-A76

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I8d433b39a5c0f9e1cef978df8a2986d7a35d3745

fix(security): workaround for CVE-2022-23960

Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.

Signed-off-by: Bipin R

fix(security): workaround for CVE-2022-23960

Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b

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fix(gpt_rme): rework delegating/undelegating sequence

The previous delegating/undelegating sequence was incorrect as per the
specification DDI0615, "Architecture Reference Manual Supplement, The
Rea

fix(gpt_rme): rework delegating/undelegating sequence

The previous delegating/undelegating sequence was incorrect as per the
specification DDI0615, "Architecture Reference Manual Supplement, The
Realm Management Extension (RME), for Armv9-A" Sections A1.1.1 and
A1.1.2

Off topic:
- cleaning the gpt_is_gpi_valid and gpt_check_pass_overlap

Change-Id: Idb64d0a2e6204f1708951137062847938ab5e0ac
Signed-off-by: Robert Wakim <robert.wakim@arm.com>

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fix(errata): workaround for Cortex-A710 2282622

Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTL

fix(errata): workaround for Cortex-A710 2282622

Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic48409822536e9eacc003300036a1f0489593020

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Merge "fix(measured-boot): add RMM entry to event_log_metadata" into integration

Merge changes I1784d643,Icb6e3699,I7805756e into integration

* changes:
fix(errata): workaround for Cortex-A510 erratum 2172148
fix(errata): workaround for Cortex-A510 erratum 2218950
fix(erra

Merge changes I1784d643,Icb6e3699,I7805756e into integration

* changes:
fix(errata): workaround for Cortex-A510 erratum 2172148
fix(errata): workaround for Cortex-A510 erratum 2218950
fix(errata): workaround for Cortex-A510 erratum 2250311

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fix(errata): workaround for Cortex-A510 erratum 2172148

Cortex-A510 erratum 2172148 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

SDEN can be f

fix(errata): workaround for Cortex-A510 erratum 2172148

Cortex-A510 erratum 2172148 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1784d643ca3d1d448340cd421facb5f229df1d22

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Merge changes I7b1498fa,I1d2ebee3,I875519ff,I8c427ef2 into integration

* changes:
fix(errata): workaround for Cortex-A510 erratum 2041909
fix(errata): workaround for Cortex-A510 erratum 2042739

Merge changes I7b1498fa,I1d2ebee3,I875519ff,I8c427ef2 into integration

* changes:
fix(errata): workaround for Cortex-A510 erratum 2041909
fix(errata): workaround for Cortex-A510 erratum 2042739
fix(errata): workaround for Cortex-A510 erratum 2288014
fix(errata): workaround for Cortex-A510 erratum 1922240

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Merge changes from topic "bug-fix" into integration

* changes:
fix(nxp-crypto): refine code to avoid hang issue for some of toolchain
build(changelog): add new scope for nxp crypto
fix(lx2): d

Merge changes from topic "bug-fix" into integration

* changes:
fix(nxp-crypto): refine code to avoid hang issue for some of toolchain
build(changelog): add new scope for nxp crypto
fix(lx2): drop erratum A-009810

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fix(measured-boot): add RMM entry to event_log_metadata

Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing

fix(measured-boot): add RMM entry to event_log_metadata

Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing RMM entry
in the event_log_metadata array.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I172f10a440797f7c9e1bc79dc72242b40c2521ea

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Merge "fix(arm): increase ARM_BL_REGIONS count" into integration

fix(arm): increase ARM_BL_REGIONS count

On RME-enabled platforms, it is currently not possible to incorporate
mapping of all bl_regions specified in bl31 setup[1] with the
ARM_BL_REGIONS macro defin

fix(arm): increase ARM_BL_REGIONS count

On RME-enabled platforms, it is currently not possible to incorporate
mapping of all bl_regions specified in bl31 setup[1] with the
ARM_BL_REGIONS macro defined to 6. Hence increased its count to 7.

[1]: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/
plat/arm/common/arm_bl31_setup.c#n380

Change-Id: Ieaa97f026ab2ae6eae22442595aa4122ba0a13c4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(errata): workaround for Cortex-A510 erratum 2042739

Cortex-A510 erratum 2042739 is a Cat B erratum that applies to revisions
r0p0, r0p1 and r0p2 and is fixed in r0p3.

SDEN can be found here:
ht

fix(errata): workaround for Cortex-A510 erratum 2042739

Cortex-A510 erratum 2042739 is a Cat B erratum that applies to revisions
r0p0, r0p1 and r0p2 and is fixed in r0p3.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1d2ebee3914396e1e298eb45bdab35ce9e194ad9

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fix(errata): workaround for Cortex-A510 erratum 2288014

Cortex-A510 erratum 2288014 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

SDEN can be f

fix(errata): workaround for Cortex-A510 erratum 2288014

Cortex-A510 erratum 2288014 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I875519ff55be90244cc3d3a7e9f7abad0fc3c2b8

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fix(errata): workaround for Cortex-A510 erratum 1922240

Cortex-A510 erratum 1922240 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1.

Since no errata framework code existed for

fix(errata): workaround for Cortex-A510 erratum 1922240

Cortex-A510 erratum 1922240 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1.

Since no errata framework code existed for A510 prior to this patch, it
has been added as well. Also some general cleanup changes in the CPU lib
makefile.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8c427ef255cb4b38ed3e5c2c7444fcef957277e4

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Merge changes from topic "x2_errata" into integration

* changes:
fix(errata): workaround for Cortex-A710 erratum 2136059
fix(errata): workaround for Cortex-A710 erratum 2267065
fix(errata): w

Merge changes from topic "x2_errata" into integration

* changes:
fix(errata): workaround for Cortex-A710 erratum 2136059
fix(errata): workaround for Cortex-A710 erratum 2267065
fix(errata): workaround for Cortex-X2 erratum 2216384
fix(errata): workaround for Cortex-X2 errata 2081180
fix(errata): workaround for Cortex-X2 errata 2017096

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fix(nxp-crypto): refine code to avoid hang issue for some of toolchain

bitfield structure maybe has strict-aliasing issue for some compiler,
for example the old code has hang issue for yocto 3.4 too

fix(nxp-crypto): refine code to avoid hang issue for some of toolchain

bitfield structure maybe has strict-aliasing issue for some compiler,
for example the old code has hang issue for yocto 3.4 toolchain, so
refine the code to avoid to use bitfield structure.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6b6d7597311240dd6d6b8ca4ce508c69332f9c68

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feat(spm): add FFA_MSG_SEND2 forwarding in SPMD

Add FF-A v1.1 indirect messaging ABI FFA_MSG_SEND2 to SPMD to allow
message forwarding across normal/secure worlds.

Change-Id: I074fbd2e4d13893925f98

feat(spm): add FFA_MSG_SEND2 forwarding in SPMD

Add FF-A v1.1 indirect messaging ABI FFA_MSG_SEND2 to SPMD to allow
message forwarding across normal/secure worlds.

Change-Id: I074fbd2e4d13893925f987cee271d49da3aaf64b
Signed-off-by: Federico Recanati <federico.recanati@arm.com>

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Merge "feat(common): add SZ_* macros" into integration

Merge changes from topic "db/exception_pstate" into integration

* changes:
test(el3-runtime): dit is retained on world switch
fix(el3-runtime): set unset pstate bits to default
refactor(el3-ru

Merge changes from topic "db/exception_pstate" into integration

* changes:
test(el3-runtime): dit is retained on world switch
fix(el3-runtime): set unset pstate bits to default
refactor(el3-runtime): add prepare_el3_entry func

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