1 /* 2 * Copyright (c) 2022, Google LLC. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X1_H 8 #define CORTEX_X1_H 9 10 /* Cortex-X1 MIDR for r1p0 */ 11 #define CORTEX_X1_MIDR U(0x411fd440) 12 13 /******************************************************************************* 14 * CPU Extended Control register specific definitions. 15 ******************************************************************************/ 16 #define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4 17 18 /******************************************************************************* 19 * CPU Power Control register specific definitions 20 ******************************************************************************/ 21 #define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22 #define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1) 23 24 #endif /* CORTEX_X1_H */ 25