1/* 2 * Copyright (c) 2022, Google LLC. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <cortex_x1.h> 9#include <cpu_macros.S> 10 11/* Hardware handled coherency */ 12#if HW_ASSISTED_COHERENCY == 0 13#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled" 14#endif 15 16/* 64-bit only core */ 17#if CTX_INCLUDE_AARCH32_REGS == 1 18#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 19#endif 20 21/* -------------------------------------------------- 22 * Errata Workaround for X1 Erratum 1821534. 23 * This applies to revision r0p0 and r1p0 of X1. 24 * Inputs: 25 * x0: variant[4:7] and revision[0:3] of current cpu. 26 * Shall clobber: x0-x17 27 * -------------------------------------------------- 28 */ 29func errata_x1_1821534_wa 30 /* Compare x0 against revision r1p0 */ 31 mov x17, x30 32 bl check_errata_1821534 33 cbz x0, 1f 34 mrs x1, CORTEX_X1_ACTLR2_EL1 35 orr x1, x1, BIT(2) 36 msr CORTEX_X1_ACTLR2_EL1, x1 37 isb 381: 39 ret x17 40endfunc errata_x1_1821534_wa 41 42func check_errata_1821534 43 /* Applies to r0p0 and r1p0 */ 44 mov x1, #0x10 45 b cpu_rev_var_ls 46endfunc check_errata_1821534 47 48/* -------------------------------------------------- 49 * Errata Workaround for X1 Erratum 1688305. 50 * This applies to revision r0p0 and r1p0 of X1. 51 * Inputs: 52 * x0: variant[4:7] and revision[0:3] of current cpu. 53 * Shall clobber: x0-x17 54 * -------------------------------------------------- 55 */ 56func errata_x1_1688305_wa 57 /* Compare x0 against revision r1p0 */ 58 mov x17, x30 59 bl check_errata_1688305 60 cbz x0, 1f 61 mrs x0, CORTEX_X1_ACTLR2_EL1 62 orr x0, x0, BIT(1) 63 msr CORTEX_X1_ACTLR2_EL1, x0 64 isb 65 661: 67 ret x17 68endfunc errata_x1_1688305_wa 69 70func check_errata_1688305 71 /* Applies to r0p0 and r1p0 */ 72 mov x1, #0x10 73 b cpu_rev_var_ls 74endfunc check_errata_1688305 75 76/* -------------------------------------------------- 77 * Errata Workaround for X1 Erratum 1827429. 78 * This applies to revision r0p0 and r1p0 of X1. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: x0-x17 82 * -------------------------------------------------- 83 */ 84func errata_x1_1827429_wa 85 /* Compare x0 against revision r1p0 */ 86 mov x17, x30 87 bl check_errata_1827429 88 cbz x0, 1f 89 mrs x0, CORTEX_X1_CPUECTLR_EL1 90 orr x0, x0, BIT(53) 91 msr CORTEX_X1_CPUECTLR_EL1, x0 92 isb 93 941: 95 ret x17 96endfunc errata_x1_1827429_wa 97 98func check_errata_1827429 99 /* Applies to r0p0 and r1p0 */ 100 mov x1, #0x10 101 b cpu_rev_var_ls 102endfunc check_errata_1827429 103 104 /* ------------------------------------------------- 105 * The CPU Ops reset function for Cortex-X1. 106 * Shall clobber: x0-x19 107 * ------------------------------------------------- 108 */ 109func cortex_x1_reset_func 110 mov x19, x30 111 bl cpu_get_rev_var 112 mov x18, x0 113 114#if ERRATA_X1_1821534 115 mov x0, x18 116 bl errata_x1_1821534_wa 117#endif 118 119#if ERRATA_X1_1688305 120 mov x0, x18 121 bl errata_x1_1688305_wa 122#endif 123 124#if ERRATA_X1_1827429 125 mov x0, x18 126 bl errata_x1_1827429_wa 127#endif 128 129 isb 130 ret x19 131endfunc cortex_x1_reset_func 132 133 /* --------------------------------------------- 134 * HW will do the cache maintenance while powering down 135 * --------------------------------------------- 136 */ 137func cortex_x1_core_pwr_dwn 138 /* --------------------------------------------- 139 * Enable CPU power down bit in power control register 140 * --------------------------------------------- 141 */ 142 mrs x0, CORTEX_X1_CPUPWRCTLR_EL1 143 orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK 144 msr CORTEX_X1_CPUPWRCTLR_EL1, x0 145 isb 146 ret 147endfunc cortex_x1_core_pwr_dwn 148 149#if REPORT_ERRATA 150/* 151 * Errata printing function for Cortex X1. Must follow AAPCS. 152 */ 153func cortex_x1_errata_report 154 stp x8, x30, [sp, #-16]! 155 156 bl cpu_get_rev_var 157 mov x8, x0 158 159 /* 160 * Report all errata. The revision-variant information is passed to 161 * checking functions of each errata. 162 */ 163 report_errata ERRATA_X1_1821534, cortex_x1, 1821534 164 report_errata ERRATA_X1_1688305, cortex_x1, 1688305 165 report_errata ERRATA_X1_1827429, cortex_x1, 1827429 166 167 ldp x8, x30, [sp], #16 168 ret 169endfunc cortex_x1_errata_report 170#endif 171 172 /* --------------------------------------------- 173 * This function provides Cortex X1 specific 174 * register information for crash reporting. 175 * It needs to return with x6 pointing to 176 * a list of register names in ascii and 177 * x8 - x15 having values of registers to be 178 * reported. 179 * --------------------------------------------- 180 */ 181.section .rodata.cortex_x1_regs, "aS" 182cortex_x1_regs: /* The ascii list of register names to be reported */ 183 .asciz "cpuectlr_el1", "" 184 185func cortex_x1_cpu_reg_dump 186 adr x6, cortex_x1_regs 187 mrs x8, CORTEX_X1_CPUECTLR_EL1 188 ret 189endfunc cortex_x1_cpu_reg_dump 190 191declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \ 192 cortex_x1_reset_func, \ 193 cortex_x1_core_pwr_dwn 194