Fix MISRA defects in some common headers

Change-Id: I8fbb4c785e7e07c7241e0c399a9b65161985c9df
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat/arm: gic: Fix macros

Change-Id: I130e35d55c474ecd80f9a825be23620d5bc1a715
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Add librom support in FVP

Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

Merge pull request #1506 from danielboulby-arm/db/SeparateCodeAndROData

Fix build for SEPARATE_CODE_AND_RODATA=0

Fix build for SEPARATE_CODE_AND_RODATA=0

TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never define

Fix build for SEPARATE_CODE_AND_RODATA=0

TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never defined for
this case. Create memory region combining code and RO data for
when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this

Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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ARM platforms: Allow board specific definition of SP stack base

The SGI platforms need to allocate memory for CPER buffers. These
platform buffers would be placed between the shared reserved memory

ARM platforms: Allow board specific definition of SP stack base

The SGI platforms need to allocate memory for CPER buffers. These
platform buffers would be placed between the shared reserved memory
and the per cpu stack memory, thus the need to redefine stack base
pointer for these platforms. This patch allows each board in ARM
platform to define the PLAT_SP_IMAGE_STACK_BASE.

Change-Id: Ib5465448b860ab7ab0f645f7cb278a67acce7be9
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>

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SGI: Include arm_spm_def.h in platform_def.h

Include arm_spm_def.h in the platform_def.h file. Without this
inclusion, we get build errors like

In file included from services/std_svc/spm/sp_setup.c

SGI: Include arm_spm_def.h in platform_def.h

Include arm_spm_def.h in the platform_def.h file. Without this
inclusion, we get build errors like

In file included from services/std_svc/spm/sp_setup.c:12:0:
services/std_svc/spm/sp_setup.c: In function 'spm_sp_setup':
services/std_svc/spm/sp_setup.c:61:57: error: 'PLAT_SPM_BUF_BASE'
undeclared (first use in this function)
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);

Now that the platform_def.h includes arm_spm_def.h, remove inclusion
of platform_def.h in arm_spm_def.h to remove the circular dependency.

Change-Id: I5225c8ca33fd8d288849524395e436c3d56daf17
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>

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Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra

Fix several MISRA defects in PSCI library

Merge pull request #1491 from jeenu-arm/misra-fix

Arm platforms: Fix type mismatch for arm_pm_idle_states

Merge pull request #1472 from danielboulby-arm/db/Reclaim

Rework page table setup for varying number of mem regions

Rework page table setup for varying number of mem regions

Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their co

Rework page table setup for varying number of mem regions

Change arm_setup_page_tables() to take a variable number of memory
regions. Remove coherent memory region from BL1, BL2 and BL2U as
their coherent memory region doesn't contain anything and
therefore has a size of 0. Add check to ensure this
doesn't change without us knowing.

Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Arm platforms: Fix type mismatch for arm_pm_idle_states

This also gets rid of MISRA violations for Rule 8.3 and 8.4.

Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc
Signed-off-by: Jeenu Viswam

Arm platforms: Fix type mismatch for arm_pm_idle_states

This also gets rid of MISRA violations for Rule 8.3 and 8.4.

Change-Id: I45bba011b16f90953dd4b260fcd58381f978eedc
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>

PSCI: Fix types of definitions

Also change header guards to fix defects of MISRA C-2012 Rule 21.1.

Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1477 from dp-arm/dp/css-ap-core

CSS: Add support for SCMI AP core config protocol

CSS: Use SCMI AP core protocol to set the warm boot entrypoint

Change-Id: Iaebbeac1a1d6fbd531e5694b95ed068b7a193e62
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

ARM platforms: Make arm_lock static

The ARM_INSTANTIATE_LOCK macro defines a lock meant to be further
manipulated using the arm_lock_init/get/release() macros. It has 2
variants, depending on the BL

ARM platforms: Make arm_lock static

The ARM_INSTANTIATE_LOCK macro defines a lock meant to be further
manipulated using the arm_lock_init/get/release() macros. It has 2
variants, depending on the BL image it is compiled for. One version
defines the lock variable with internal linkage whereas the other one,
with external linkage.

Code that uses these macros is not compliant with MISRA rule 8.4 because
when using the external linkage version, there is no visible declaration
for the lock variable.

This patch defines the arm_lock variable with internal linkage in both
cases. This fits well the way these macros are used in the code today,
where the lock is not used outside of the translation unit it is
defined in.

Change-Id: I213a74a2a6088a4f1e9a61a319ca7579c2001320
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Remove string concatenation in assembler files

Clang assembler doesn't support concatenation of adjacent strings.

Change-Id: I092a1e30c137d431c6adcc13519fc2d595f92f14
Signed-off-by: Roberto Vargas

Remove string concatenation in assembler files

Clang assembler doesn't support concatenation of adjacent strings.

Change-Id: I092a1e30c137d431c6adcc13519fc2d595f92f14
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Use ALIGN instead of NEXT in linker scripts

Clang linker doesn't support NEXT. As we are not using the MEMORY command
to define discontinuous memory for the output file in any of the linker
scripts,

Use ALIGN instead of NEXT in linker scripts

Clang linker doesn't support NEXT. As we are not using the MEMORY command
to define discontinuous memory for the output file in any of the linker
scripts, ALIGN and NEXT are equivalent.

Change-Id: I867ffb9c9a76d4e81c9ca7998280b2edf10efea0
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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ARM Platforms: Update CNTFRQ register in CNTCTLBase frame

Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase
frame of the system timer. ARM ARM states that "The instance of
the register

ARM Platforms: Update CNTFRQ register in CNTCTLBase frame

Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase
frame of the system timer. ARM ARM states that "The instance of
the register in the CNTCTLBase frame must be programmed with this
value as part of system initialization."

The psci_arch_setup() updates the CNTFRQ system register but
according to the ARM ARM, this instance of the register is
independent of the memory mapped instance. This is only an issue
for Normal world software which relies on the memory mapped
instance rather than the system register one.

This patch resolves the issue for ARM platforms.

The patch also solves a related issue on Juno, wherein
CNTBaseN.CNTFRQ can be written and does not reflect the value of
the register in CNTCTLBase frame. Hence this patch additionally
updates CNTFRQ register in the Non Secure frame of the CNTBaseN.

Fixes ARM-Software/tf-issues#593

Change-Id: I09cebb6633688b34d5b1bc349fbde4751025b350
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1418 from antonio-nino-diaz-arm/an/arm-multi-console

plat/arm: Migrate AArch64 port to the multi console driver

plat/arm: Migrate AArch64 port to the multi console driver

The old API is deprecated and will eventually be removed.

Arm platforms now use the multi console driver for boot and runtime
consoles. Ho

plat/arm: Migrate AArch64 port to the multi console driver

The old API is deprecated and will eventually be removed.

Arm platforms now use the multi console driver for boot and runtime
consoles. However, the crash console uses the direct console API because
it doesn't need any memory access to work. This makes it more robust
during crashes.

The AArch32 port of the Trusted Firmware doesn't support this new API
yet, so it is only enabled in AArch64 builds. Because of this, the
common code must maintain compatibility with both systems. SP_MIN
doesn't have to be updated because it's only used in AArch32 builds.
The TSP is only used in AArch64, so it only needs to support the new
API without keeping support for the old one.

Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this
causes the UARTs to reset (except for the one used by the TSP). This
means that they must be unregistered when suspending and re-registered
when resuming. This wasn't a problem with the old driver because it just
restarted the UART, and there were no problems associated with
registering and unregistering consoles.

The size reserved for BL2 has been increased.

Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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SPM: Treat SP xlat tables the same as others

The translation tables allocated for the Secure Partition do not need
to be treated as a special case. They can be put amongst the other
tables mapping B

SPM: Treat SP xlat tables the same as others

The translation tables allocated for the Secure Partition do not need
to be treated as a special case. They can be put amongst the other
tables mapping BL31's general purpose memory. They will be mapped with
the same attributes as them, which is fine.

The explicit alignment constraint in BL31's linker script to pad the
last page of memory allocated to the Secure Partition's translation
tables is useless too, as page tables are per se pages, thus their
end address is naturally aligned on a page-boundary.

In fact, this patch does not change the existing behaviour. Since
patch 22282bb68a31 ("SPM: Move all SP-related info to SP context
struct"), the secure_partition.c file has been renamed into sp_xlat.c
but the linker script has not been properly updated. As a result, the
SP translation tables are not specifically put at the start of the
xlat_table linker section, the __SP_IMAGE_XLAT_TABLES_START__/_END__
symbols have the same value, the size of the resulting mmap_region
covering these xlat tables is 0 and so it is ignored.

Change-Id: I4cf0a4cc090298811cca53fc9cee74df0f2b1512
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Adjust BL2_AT_EL3 memory layout

For the BL2_AT_EL3 configuration, move BL2 higher up to make more
space for BL31. Adjust the BL31 limit to be up to BL2 base. This is
because BL2 is always resident

Adjust BL2_AT_EL3 memory layout

For the BL2_AT_EL3 configuration, move BL2 higher up to make more
space for BL31. Adjust the BL31 limit to be up to BL2 base. This is
because BL2 is always resident for the BL2_AT_EL3 configuration and
thus we cannot overlay it with BL31.

Change-Id: I71e89863ed48f5159e8b619f49c7c73b253397aa
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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ARM platforms: Move BL31 below BL2 to enable BL2 overlay

The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expe

ARM platforms: Move BL31 below BL2 to enable BL2 overlay

The patch changes the layout of BL images in memory to enable
more efficient use of available space. Previously BL31 was loaded
with the expectation that BL2 memory would be reclaimed by BL32
loaded in SRAM. But with increasing memory requirements in the
firmware, we can no longer fit BL32 in SRAM anymore which means the
BL2 memory is not reclaimed by any runtime image. Positioning BL2
below BL1-RW and above BL31 means that the BL31 NOBITS can be
overlaid on BL2 and BL1-RW.

This patch also propogates the same memory layout to BL32 for AArch32
mode. The reset addresses for the following configurations are also
changed :
* When RESET_TO_SP_MIN=1 for BL32 in AArch32 mode
* When BL2_AT_EL3=1 for BL2

The restriction on BL31 to be only in DRAM when SPM is enabled
is now removed with this change. The update to the firmware design
guide for the BL memory layout is done in the following patch.

Change-Id: Icca438e257abe3e4f5a8215f945b9c3f9fbf29c9
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1395 from antonio-nino-diaz-arm/an/spm-refactor

SPM: Refactor codebase