1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <platform.h> 17 #include <ras.h> 18 19 /* 20 * Placeholder variables for copying the arguments that have been passed to 21 * BL31 from BL2. 22 */ 23 static entry_point_info_t bl32_image_ep_info; 24 static entry_point_info_t bl33_image_ep_info; 25 26 /* 27 * Check that BL31_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 28 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 29 */ 30 CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 31 32 /* Weak definitions may be overridden in specific ARM standard platform */ 33 #pragma weak bl31_early_platform_setup2 34 #pragma weak bl31_platform_setup 35 #pragma weak bl31_plat_arch_setup 36 #pragma weak bl31_plat_get_next_image_ep_info 37 38 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 39 BL31_BASE, \ 40 BL31_END - BL31_BASE, \ 41 MT_MEMORY | MT_RW | MT_SECURE) 42 43 /******************************************************************************* 44 * Return a pointer to the 'entry_point_info' structure of the next image for the 45 * security state specified. BL33 corresponds to the non-secure image type 46 * while BL32 corresponds to the secure image type. A NULL pointer is returned 47 * if the image does not exist. 48 ******************************************************************************/ 49 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 50 { 51 entry_point_info_t *next_image_info; 52 53 assert(sec_state_is_valid(type)); 54 next_image_info = (type == NON_SECURE) 55 ? &bl33_image_ep_info : &bl32_image_ep_info; 56 /* 57 * None of the images on the ARM development platforms can have 0x0 58 * as the entrypoint 59 */ 60 if (next_image_info->pc) 61 return next_image_info; 62 else 63 return NULL; 64 } 65 66 /******************************************************************************* 67 * Perform any BL31 early platform setup common to ARM standard platforms. 68 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 69 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 70 * done before the MMU is initialized so that the memory layout can be used 71 * while creating page tables. BL2 has flushed this information to memory, so 72 * we are guaranteed to pick up good data. 73 ******************************************************************************/ 74 #if LOAD_IMAGE_V2 75 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 76 uintptr_t hw_config, void *plat_params_from_bl2) 77 #else 78 void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config, 79 uintptr_t hw_config, void *plat_params_from_bl2) 80 #endif 81 { 82 /* Initialize the console to provide early debug support */ 83 arm_console_boot_init(); 84 85 #if RESET_TO_BL31 86 /* There are no parameters from BL2 if BL31 is a reset vector */ 87 assert(from_bl2 == NULL); 88 assert(plat_params_from_bl2 == NULL); 89 90 # ifdef BL32_BASE 91 /* Populate entry point information for BL32 */ 92 SET_PARAM_HEAD(&bl32_image_ep_info, 93 PARAM_EP, 94 VERSION_1, 95 0); 96 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 97 bl32_image_ep_info.pc = BL32_BASE; 98 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 99 # endif /* BL32_BASE */ 100 101 /* Populate entry point information for BL33 */ 102 SET_PARAM_HEAD(&bl33_image_ep_info, 103 PARAM_EP, 104 VERSION_1, 105 0); 106 /* 107 * Tell BL31 where the non-trusted software image 108 * is located and the entry state information 109 */ 110 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 111 112 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 113 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 114 115 # if ARM_LINUX_KERNEL_AS_BL33 116 /* 117 * According to the file ``Documentation/arm64/booting.txt`` of the 118 * Linux kernel tree, Linux expects the physical address of the device 119 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 120 * must be 0. 121 */ 122 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 123 bl33_image_ep_info.args.arg1 = 0U; 124 bl33_image_ep_info.args.arg2 = 0U; 125 bl33_image_ep_info.args.arg3 = 0U; 126 # endif 127 128 #else /* RESET_TO_BL31 */ 129 130 /* 131 * In debug builds, we pass a special value in 'plat_params_from_bl2' 132 * to verify platform parameters from BL2 to BL31. 133 * In release builds, it's not used. 134 */ 135 assert(((unsigned long long)plat_params_from_bl2) == 136 ARM_BL31_PLAT_PARAM_VAL); 137 138 # if LOAD_IMAGE_V2 139 /* 140 * Check params passed from BL2 should not be NULL, 141 */ 142 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 143 assert(params_from_bl2 != NULL); 144 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 145 assert(params_from_bl2->h.version >= VERSION_2); 146 147 bl_params_node_t *bl_params = params_from_bl2->head; 148 149 /* 150 * Copy BL33 and BL32 (if present), entry point information. 151 * They are stored in Secure RAM, in BL2's address space. 152 */ 153 while (bl_params != NULL) { 154 if (bl_params->image_id == BL32_IMAGE_ID) 155 bl32_image_ep_info = *bl_params->ep_info; 156 157 if (bl_params->image_id == BL33_IMAGE_ID) 158 bl33_image_ep_info = *bl_params->ep_info; 159 160 bl_params = bl_params->next_params_info; 161 } 162 163 if (bl33_image_ep_info.pc == 0U) 164 panic(); 165 166 # else /* LOAD_IMAGE_V2 */ 167 168 /* 169 * Check params passed from BL2 should not be NULL, 170 */ 171 assert(from_bl2 != NULL); 172 assert(from_bl2->h.type == PARAM_BL31); 173 assert(from_bl2->h.version >= VERSION_1); 174 175 /* Dynamic Config is not supported for LOAD_IMAGE_V1 */ 176 assert(soc_fw_config == 0U); 177 assert(hw_config == 0U); 178 179 /* 180 * Copy BL32 (if populated by BL2) and BL33 entry point information. 181 * They are stored in Secure RAM, in BL2's address space. 182 */ 183 if (from_bl2->bl32_ep_info) 184 bl32_image_ep_info = *from_bl2->bl32_ep_info; 185 bl33_image_ep_info = *from_bl2->bl33_ep_info; 186 187 # endif /* LOAD_IMAGE_V2 */ 188 #endif /* RESET_TO_BL31 */ 189 } 190 191 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 192 u_register_t arg2, u_register_t arg3) 193 { 194 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 195 196 /* 197 * Initialize Interconnect for this cluster during cold boot. 198 * No need for locks as no other CPU is active. 199 */ 200 plat_arm_interconnect_init(); 201 202 /* 203 * Enable Interconnect coherency for the primary CPU's cluster. 204 * Earlier bootloader stages might already do this (e.g. Trusted 205 * Firmware's BL1 does it) but we can't assume so. There is no harm in 206 * executing this code twice anyway. 207 * Platform specific PSCI code will enable coherency for other 208 * clusters. 209 */ 210 plat_arm_interconnect_enter_coherency(); 211 } 212 213 /******************************************************************************* 214 * Perform any BL31 platform setup common to ARM standard platforms 215 ******************************************************************************/ 216 void arm_bl31_platform_setup(void) 217 { 218 /* Initialize the GIC driver, cpu and distributor interfaces */ 219 plat_arm_gic_driver_init(); 220 plat_arm_gic_init(); 221 222 #if RESET_TO_BL31 223 /* 224 * Do initial security configuration to allow DRAM/device access 225 * (if earlier BL has not already done so). 226 */ 227 plat_arm_security_setup(); 228 229 #if defined(PLAT_ARM_MEM_PROT_ADDR) 230 arm_nor_psci_do_dyn_mem_protect(); 231 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 232 233 #endif /* RESET_TO_BL31 */ 234 235 /* Enable and initialize the System level generic timer */ 236 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 237 CNTCR_FCREQ(0U) | CNTCR_EN); 238 239 /* Allow access to the System counter timer module */ 240 arm_configure_sys_timer(); 241 242 /* Initialize power controller before setting up topology */ 243 plat_arm_pwrc_setup(); 244 245 #if RAS_EXTENSION 246 ras_init(); 247 #endif 248 } 249 250 /******************************************************************************* 251 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 252 * standard platforms 253 * Perform BL31 platform setup 254 ******************************************************************************/ 255 void arm_bl31_plat_runtime_setup(void) 256 { 257 #if MULTI_CONSOLE_API 258 console_switch_state(CONSOLE_FLAG_RUNTIME); 259 #else 260 console_uninit(); 261 #endif 262 263 /* Initialize the runtime console */ 264 arm_console_runtime_init(); 265 } 266 267 void bl31_platform_setup(void) 268 { 269 arm_bl31_platform_setup(); 270 } 271 272 void bl31_plat_runtime_setup(void) 273 { 274 arm_bl31_plat_runtime_setup(); 275 } 276 277 /******************************************************************************* 278 * Perform the very early platform specific architectural setup shared between 279 * ARM standard platforms. This only does basic initialization. Later 280 * architectural setup (bl31_arch_setup()) does not do anything platform 281 * specific. 282 ******************************************************************************/ 283 void arm_bl31_plat_arch_setup(void) 284 { 285 286 #define ARM_MAP_BL_ROMLIB MAP_REGION_FLAT( \ 287 BL31_BASE, \ 288 BL31_END - BL31_BASE, \ 289 MT_MEMORY | MT_RW | MT_SECURE) 290 291 const mmap_region_t bl_regions[] = { 292 MAP_BL31_TOTAL, 293 ARM_MAP_BL_RO, 294 #if USE_ROMLIB 295 ARM_MAP_ROMLIB_CODE, 296 ARM_MAP_ROMLIB_DATA, 297 #endif 298 #if USE_COHERENT_MEM 299 ARM_MAP_BL_COHERENT_RAM, 300 #endif 301 {0} 302 }; 303 304 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 305 306 enable_mmu_el3(0); 307 308 arm_setup_romlib(); 309 } 310 311 void bl31_plat_arch_setup(void) 312 { 313 arm_bl31_plat_arch_setup(); 314 } 315