feat(handoff): add additional TE tags

`TL_TAG_EXEC_EP_INFO64` type entries represent the `entry_point_info_t`
data structure. This structure provides the consumer with the execution
environment of a

feat(handoff): add additional TE tags

`TL_TAG_EXEC_EP_INFO64` type entries represent the `entry_point_info_t`
data structure. This structure provides the consumer with the execution
environment of an image. This is needed primarily in BL31 to execute
subsequent images i.e. BL32, BL33, or NT FW.

`TL_TAG_DT_SPMC_MANIFEST` holds the SPMC (Secure Partition Manager Core)
manifest image which is in DT format.

Change-Id: I80c4a72d639851457bc3c9b158b2e56041e8b29a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "mte_fixes" into integration

* changes:
build(changelog): move mte to mte2
refactor(mte): remove mte, mte_perm

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Sign

chore: rename Poseidon to Neoverse V3

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(cpus): workaround for Cortex-A720 erratum 2940794" into integration

fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of

fix(cpus): workaround for Cortex-A720 erratum 2940794

Cortex-A720 erratum 2940794 is a Cat B erratum that is present
in revision r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[37] of the CPUACTLR2_EL1 to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I1488802e0ec7c16349c9633bb45de4d0e1faa9ad
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(S

fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(Statistical Profiling Extension) is enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is enabled, ENABLE_SPE_FOR_NS=1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "refactor(cm): couple el2 registers with dependent feature flags" into integration

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level for region validity
feat(tc): add dummy TRNG support to be able to boot pVMs
feat(tc): get the parent component provided DPE context_handle
feat(tc): share DPE context handle with child component
feat(tc): add DPE context handle node to device tree
feat(tc): add DPE backend to the measured boot framework
feat(auth): add explicit entries for key OIDs
feat(dice): add DPE driver to measured boot
feat(dice): add client API for DICE Protection Environment
feat(dice): add QCBOR library as a dependency of DPE
feat(dice): add typedefs from the Open DICE repo
docs(changelog): add 'dice' scope
refactor(tc): align image identifier string macros
refactor(fvp): align image identifier string macros
refactor(imx8m): align image identifier string macros
refactor(qemu): align image identifier string macros
fix(measured-boot): add missing image identifier string
refactor(measured-boot): move metadata size macros to a common header
refactor(measured-boot): move image identifier strings to a common header

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refactor(cm): couple el2 registers with dependent feature flags

Currently the EL2 part of the context structure (el2_sysregs_t), is
mostly feature dependent.

For instance, CTX_HCRX_EL2 is only need

refactor(cm): couple el2 registers with dependent feature flags

Currently the EL2 part of the context structure (el2_sysregs_t), is
mostly feature dependent.

For instance, CTX_HCRX_EL2 is only needed when FEAT_HCX
(ENABLE_FEAT_HCX=1) is set, but the entry is unconditionally added
in the EL2 context structure and thereby consuming memory even in
build configurations where FEAT_HCX is disabled.

Henceforth, all such context entries should be coupled/tied with
their respective feature enables and be optimized away when unused.
This would reduce the context memory allocation for platforms, that
dont enable/support all the architectural features at once.

Further, converting the assembly context-offset entries into
a c structure relies on garbage collection of the linker
removing unreferenced structures from memory, as well as aiding
in readability and future maintenance.

Change-Id: I0cf49498ee3033cb6f3ee3810331121b26627783
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2344187

Cortex-A715 erratum 2344187 is a Cat B erratum that applies to r0p0,
r1p0 and is fixed in r1p1. The workaround is to set GCR_EL1.RRND to
0b1, an

fix(cpus): workaround for Cortex-A715 erratum 2344187

Cortex-A715 erratum 2344187 is a Cat B erratum that applies to r0p0,
r1p0 and is fixed in r1p1. The workaround is to set GCR_EL1.RRND to
0b1, and apply an implementation specific patch sequence.

SDEN: https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: I78ea39a91254765c964bff89f771af33b23f29c1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(dice): add cert_id argument to dpe_derive_context()

This custom argument is meant to simplify to group
components into certificates. Components with
the same cert_id contribute to the same cert

feat(dice): add cert_id argument to dpe_derive_context()

This custom argument is meant to simplify to group
components into certificates. Components with
the same cert_id contribute to the same certificate
regardless of the load order or the structure of the
derivation tree. This argument aims to flatten the tree
structure and make it easy to include branches or
subtrees in the main derivation line.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I83c4abc399616063a5eb04792d603899f7513627

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feat(dice): add client API for DICE Protection Environment

RSS provides the DICE Protection Environment
service (DPE). It partially implements the
DPE specification from TCG.

As a DPE profile, it s

feat(dice): add client API for DICE Protection Environment

RSS provides the DICE Protection Environment
service (DPE). It partially implements the
DPE specification from TCG.

As a DPE profile, it supports the
Open Profile for DICE specification.
https://pigweed.googlesource.com/open-dice/+/refs/heads/main/docs/specification.md

In order to communicate with the service, commands
must be CBOR encoded.
The API implementation:
- Expose a C API to the upper layer,
- Do the CBOR encoding, decoding of the DPE
commands,
- Rely on the PSA framework to communicate
with the RSS through an MHU.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I26a08f0c7cbffe07e725a7defbb6c60fd7735efe

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feat(dice): add typedefs from the Open DICE repo

The DPE implementation in RSS is aligned with the
Open Profile for DICE specification:
https://pigweed.googlesource.com/open-dice/

Type definitions

feat(dice): add typedefs from the Open DICE repo

The DPE implementation in RSS is aligned with the
Open Profile for DICE specification:
https://pigweed.googlesource.com/open-dice/

Type definitions are needed to specify the input
values for the DPE service. Instead of mandating to
clone the entire open-dice repo, the following file
is copied from the repository:
https://pigweed.googlesource.com/open-dice/+/refs/heads/main/include/dice/dice.h
Git SHA of the source version: cf549422e39da872d64993be944099ac62ba22a9

This is external code, with Apache 2.0 license, therefore
the license.rst is updated accordingly and a copy of this
license is also added.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: Ie84b8483034819d1143fe0ec812e66514ac7d4cb

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refactor(measured-boot): move metadata size macros to a common header

The max size macros of metadata elements are shared across
multiple measured boot backends: rss-measured-boot, dpe.

Increase th

refactor(measured-boot): move metadata size macros to a common header

The max size macros of metadata elements are shared across
multiple measured boot backends: rss-measured-boot, dpe.

Increase the SW_TYPE_MAX_SIZE to be able to accomodate
all macro.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic9004a36ef1df96c70a4f7adf7bb86dc27dd307c

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Merge changes I1415e402,Ia92cc693,I7a42f72e,I6e75659e,I4c6136c5, ... into integration

* changes:
refactor(tc): correlate secure world addresses with platform_def
feat(tc): add memory node in the

Merge changes I1415e402,Ia92cc693,I7a42f72e,I6e75659e,I4c6136c5, ... into integration

* changes:
refactor(tc): correlate secure world addresses with platform_def
feat(tc): add memory node in the device tree
feat(tc): pass the DTB address to BL33 in R0
feat(tc): add arm_ffa node in dts
chore(tc): add dummy entropy to speed up the Linux boot
feat(tc): choose the DPU address and irq based on the target
feat(tc): add SCMI power domain and IOMMU toggles
refactor(tc): move the FVP RoS to a separate file
feat(tc): factor in FVP/FPGA differences
feat(tc): introduce an FPGA subvariant and TC3 CPUs
feat(tc): add TC3 platform definitions
refactor(tc): sanitise the device tree
feat(tc): add PMU entry
feat(tc): allow booting from DRAM
chore(tc): remove unused hdlcd
feat(tc): add firmware update secure partition
feat(tc): add spmc manifest with trusty sp
refactor(tc): unify all the spmc manifests
feat(arm): add trusty_sp_fw_config build option
fix(tc): do not enable MPMM and Aux AMU counters always
fix(tc): correct interrupts
feat(tc): interrupt numbers for `smmu_700`
feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain

show more ...

Merge "fix(psa): fix static check failure" into integration

feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't com

feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't come naturally. To avoid this, add the memory node such that it
uses the macros defined in platform_def.

By doing this we can put u-boot out of its misery in trying to come up
with the correct memory node and tf-a's device tree becomes complete.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia92cc6931abb12be2856ac3fb1455e4f3005b326

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refactor(context-mgmt): move EL1 save/restore routines into C

Similar to the refactoring process followed for EL2 system registers,
moving the save and restore routines of EL1 system registers into

refactor(context-mgmt): move EL1 save/restore routines into C

Similar to the refactoring process followed for EL2 system registers,
moving the save and restore routines of EL1 system registers into C
file, thereby reducing assembly code.

Change-Id: Ib59fbbe2eef2aa815effe854cf962fc4ac62a2ae
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(psa): fix static check failure

Address the coding style issue that arose from patch [1], which
was inadvertently overlooked during the CI check.

[1]: https://review.trustedfirmware.org/c/TF-A/t

fix(psa): fix static check failure

Address the coding style issue that arose from patch [1], which
was inadvertently overlooked during the CI check.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/26263

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I280766fddf0e9e366bb2376c52a6907093b0d958

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refactor(tc): update platform tests

Update the TC's platform test Makefile and related common definitions
to correspond to newer TF-M code (commit hash: 4ab7a20).

Change-Id: I6ef3effe194a780a0533f9

refactor(tc): update platform tests

Update the TC's platform test Makefile and related common definitions
to correspond to newer TF-M code (commit hash: 4ab7a20).

Change-Id: I6ef3effe194a780a0533f9c0c2eab9d0f4efc1fc
Signed-off-by: David Vincze <david.vincze@arm.com>

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feat(rss): add defines for 'type' range and use them in psa_call()

Update the 'type' parameter checking according to changes
on RSS's (TF-M) side: 40b09ba1 [1]

[1]: https://git.trustedfirmware.org/

feat(rss): add defines for 'type' range and use them in psa_call()

Update the 'type' parameter checking according to changes
on RSS's (TF-M) side: 40b09ba1 [1]

[1]: https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/commit/?id=40b09ba1e4a7a4f726f98700eab7e4e4d8e95dcf

Change-Id: I8487e8ab24aa2dd080b5bb8f2f5c7e8fc15cf211
Signed-off-by: David Vincze <david.vincze@arm.com>

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Merge changes from topic "ja/spm_rme" into integration

* changes:
docs: change FVP argument in RME configuration
feat(fvp): added calls to unprotect/protect memory

Merge "fix(cpus): workaround for Cortex-A715 erratum 2561034" into integration