fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://de

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Id65d5ba41b96648b07c09df77fb25cc4bdb50800
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/resto

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

The mitigation is implemented in commit 7455cd172 and this patch should be applied on top of it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic0ad68f7bd393bdc03343d5ba815adb23bf6a24d

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fix(security): fix spectre bhb loop count for Cortex-A720

fix@c2a15217c3053117f4d39233002cb1830fa96670
based on https://developer.arm.com/documentation/110280/latest/
Spectre-BHB loop count K value

fix(security): fix spectre bhb loop count for Cortex-A720

fix@c2a15217c3053117f4d39233002cb1830fa96670
based on https://developer.arm.com/documentation/110280/latest/
Spectre-BHB loop count K value for Cortex-A720 is 38.

Change-Id: Ib6862dbed55e5ffcd0fcd58b45a88cf925c54154
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102

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fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to clear the WFE_RET_CTRL and WFI_RET_CTRL fields
in CPUPWRCTLR_EL1 to disable full retention.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: I9786ab8843a2eab45e650c6af50b6933481527ec
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit

fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit 3 in CPUACTLR3_EL1 which will have no
performance impact, but will increase power consumption by 0.3-0.5%.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ia76ba2431d76f14c08b95a998806986190d682c3
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUA

fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUACTLR2_EL1 which will correct
the instruction fetch stream with no performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ifec40dee2f7e42c56c9ed447b6b1997b170f9453
Signed-off-by: John Powell <john.powell@arm.com>

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chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "feat(cpus): fix external LLC presence bit in Neoverse N3" into integration

feat(cpus): fix external LLC presence bit in Neoverse N3

Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
ext

feat(cpus): fix external LLC presence bit in Neoverse N3

Unlike Neoverse N2, Neoverse N3 incorporates the External LLC presence
bit in CPUECTLR2_EL1.SW_EXT_LLC. In addition, the default value is
external LLC in Neoverse N3, so the bit will be cleared when
NEOVERSE_Nx_EXTERNAL_LLC is not enabled.

Change-Id: I1182aba5423e74748efd2571cc3817634ada748d
Signed-off-by: Younghyun Park <younghyunpark@google.com>

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feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
S

feat(cpus): add support for Canyon CPU

Add basic CPU library code to support the Canyon CPU.

Change-Id: I82edc4384c4fe35ec2cf6b4bfd877a24ad8725dc
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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fix(cpus): workaround for Cortex-X4 erratum 3887999

Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.

The erratum can be avoided by setting CPUAC

fix(cpus): workaround for Cortex-X4 erratum 3887999

Cortex-X4 erratum 3887999 is a Cat B erratum that applies
to all revisions <= r0p3 and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1 which will
disable linking multiple Non-Cacheable or Device GRE loads to the same
read request for the cache-line. This might have a significant
performance impact to Non-cacheable and Device GRE read bandwidth for
streaming scenarios

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I851746b7b430eac85184c8d402d1aa5bb3c94a8e

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fix(cpus): workaround for Cortex-X2 erratum 1934260

Cortex-X2 erratum 1934260 is a Cat B erratum that applies only
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[25:18

fix(cpus): workaround for Cortex-X2 erratum 1934260

Cortex-X2 erratum 1934260 is a Cat B erratum that applies only
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUECTLR_EL1[25:18] to 0xFF. This
workaround will result in reduced performance for workloads
that benefit from write streaming.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I180d38fee27175dc8ac5fa6726e5b71c3340285f
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 1901946

Cortex-X2 erratum 1901946 is a Cat B erratum that applies to
revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This

fix(cpus): workaround for Cortex-X2 erratum 1901946

Cortex-X2 erratum 1901946 is a Cat B erratum that applies to
revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This has a small
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I5a65db60f06982191994db49815419c4d72506cf
Signed-off-by: John Powell <john.powell@arm.com>

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feat(psci): check that CPUs handled a pabandon

Up to now PSCI assumed that if a pabandon happened then the CPU driver
will have handled it. This patch adds a simple protocol to make sure
that this i

feat(psci): check that CPUs handled a pabandon

Up to now PSCI assumed that if a pabandon happened then the CPU driver
will have handled it. This patch adds a simple protocol to make sure
that this is indeed the case. The chosen method is with a return value
that is highly unlikely on cores that are unaware of pabandon (x0 will
be primed with 1 and if used should be overwritten with the value of
CPUPWRCTLR_EL1 which should have its last bit set to power off and its
top bits RES0; the ACK value is chosen to be the exact opposite). An
alternative method would have been to add a field in cpu_ops, however
that would have required more major refactoring across many cpus and
would have taken up more memory on older platforms, so it was not
chosen.

Change-Id: I5826c0e4802e104d295c4ecbd80b5f676d2cd871
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

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Merge changes I1fae91a5,I54793492,I703f0e6e into integration

* changes:
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): w

Merge changes I1fae91a5,I54793492,I703f0e6e into integration

* changes:
fix(cpus): workaround for Cortex-A710 erratum 1917258
fix(cpus): workaround for Cortex-A710 erratum 1916945
fix(cpus): workaround for Cortex-A710 erratum 1901946

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feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum

feat(errata): implement workaround for DSU-120 erratum 2900952

DSU Erratum 2900952 is a Cat B erratum that applies to some
DSU-120 implementations of revision r2p0 and is fixed in r2p1.
This erratum is fixed in certain implementations of r2p0 which can be
determined by reading the IMP_CLUSTERREVIDR_EL1[1] register field
where a set bit indicates that the erratum is fixed in this part.

The workaround is to set the CLUSTERACTLR_EL1 bits [21:20] to 0x3
which ignores CBusy from the system interconnect and
setting CLUSTERACTLR_EL1 bit [8] to 1 to assert CBusy from DSU to
all the cores when DSU is busy.

SDEN: https://developer.arm.com/documentation/SDEN-2453103/1200/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I87aa440ab5c35121aff703032f5cf7a62d0b0bb4

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fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15].

fix(cpus): workaround for Cortex-A710 erratum 1901946

Cortex-A710 erratum 1901946 is a Cat B erratum that applies
to revision r1p0 and is fixed in r2p0.

The workaround is to set CPUACTLR4_EL1[15]. This has a slight
performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101

Change-Id: I703f0e6ee122e44a9bc284d90f1465039e3b40e4
Signed-off-by: John Powell <john.powell@arm.com>

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feat(cpus): update cpu_check_csv2 check

Update the cpu_check_csv2 logic to allow ID_AA64PFR0_EL1.CSV2
values up to 3. With the introduction of FEAT_CSV2_3,
the architectural limit for CSV2 has been

feat(cpus): update cpu_check_csv2 check

Update the cpu_check_csv2 logic to allow ID_AA64PFR0_EL1.CSV2
values up to 3. With the introduction of FEAT_CSV2_3,
the architectural limit for CSV2 has been extended,
making values from 0 to 3 valid.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8473047ed4ad759b7b506161a76774ac21555d31

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Merge changes I005586ef,I0d4d74bc into integration

* changes:
fix(cpufeat): replace "bti" mnemonic with hint instructions
fix(cpufeat): improve xpaci wrapper

fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
a

fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
assembly code. Binutils v2.35 have relaxed this, since "bti" is in the
hint space, so is ignored on older cores and does NOT require a BTI
enabled core to execute.

To not exclude those older binutils versions (as shipped with Ubuntu
20.04), use the "hint" encoding for the "bti" instructions, which are
accepted regardless of the minimum architecture revision. Hide this
encoding in a macro, to make the "bti" usage more readable in the
source code.

Change-Id: I005586efd8974a3f2c7202896c881bb5fed07eea
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* cal

refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* calls.

Previously, EXTRA functions were individually implemented for
each SMCCC_ARCH_WORKAROUND_*, an approach that becomes unmanageable
with the increasing number of workarounds.
By looking up erratum entries for CVE check, the process is streamlined,
reducing overhead associated with creating and
maintaining EXTRA functions for each new workaround.

New Errata entries are created for SMC workarounds and
that is used to target cpus that are uniquely impacted
by SMC workarounds.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I873534e367a35c99461d0a616ff7bf856a0000af

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fix(cpus): fix clang compilation issue

A potential problem with clang version < 17 can cause resolving nested
'cfi_startproc' to fail compilation.

So add a variant of check_errara/reset_macros that

fix(cpus): fix clang compilation issue

A potential problem with clang version < 17 can cause resolving nested
'cfi_startproc' to fail compilation.

So add a variant of check_errara/reset_macros that is compatible with
clang version < 17 to ignore `cfi_startproc` and `cfi_endproc`.

This wouldn't cause any performance issue and will not affect any
functional behaviour.

Change-Id: I46147af2dd0accd5be14ddb26dea03bb2f87cba8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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