1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v2 26 27workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 28 /* Disable retention control for WFI and WFE. */ 29 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 30 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 31 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 32 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 33 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 34 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 35workaround_reset_end neoverse_v2, ERRATUM(2618597) 36 37check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 38 39workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 40 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 41 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 42workaround_reset_end neoverse_v2, ERRATUM(2662553) 43 44check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 45 46workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 47 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 48workaround_reset_end neoverse_v2, ERRATUM(2719105) 49 50check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 51 52workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 53 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 54 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 55workaround_reset_end neoverse_v2, ERRATUM(2743011) 56 57check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 58 59workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 60 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 61workaround_reset_end neoverse_v2, ERRATUM(2779510) 62 63check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 64 65workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 66 /* dsb before isb of power down sequence */ 67 dsb sy 68workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 69 70check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 71 72workaround_reset_start neoverse_v2, ERRATUM(3841324), ERRATA_V2_3841324 73 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, BIT(1) 74workaround_reset_end neoverse_v2, ERRATUM(3841324) 75 76check_erratum_ls neoverse_v2, ERRATUM(3841324), CPU_REV(0, 1) 77 78workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 79#if IMAGE_BL31 80 /* 81 * The Neoverse-V2 generic vectors are overridden to apply errata 82 * mitigation on exception entry from lower ELs. 83 */ 84 override_vector_table wa_cve_vbar_neoverse_v2 85#endif /* IMAGE_BL31 */ 86workaround_reset_end neoverse_v2, CVE(2022,23960) 87 88check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 89 90/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 91workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 92 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 93workaround_reset_end neoverse_v2, CVE(2024, 5660) 94 95check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 96 97#if WORKAROUND_CVE_2022_23960 98 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 99#endif /* WORKAROUND_CVE_2022_23960 */ 100 101workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 102 /* --------------------------------- 103 * Sets BIT41 of CPUACTLR6_EL1 which 104 * disables L1 Data cache prefetcher 105 * --------------------------------- 106 */ 107 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 108workaround_reset_end neoverse_v2, CVE(2024, 7881) 109 110check_erratum_chosen neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 111 112 /* ---------------------------------------------------- 113 * HW will do the cache maintenance while powering down 114 * ---------------------------------------------------- 115 */ 116func neoverse_v2_core_pwr_dwn 117 /* --------------------------------------------------- 118 * Enable CPU power down bit in power control register 119 * --------------------------------------------------- 120 */ 121 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 122 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 123 124 isb 125 ret 126endfunc neoverse_v2_core_pwr_dwn 127 128cpu_reset_func_start neoverse_v2 129 /* Disable speculative loads */ 130 msr SSBS, xzr 131 132#if NEOVERSE_Vx_EXTERNAL_LLC 133 /* Some systems may have External LLC, core needs to be made aware */ 134 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 135#endif 136cpu_reset_func_end neoverse_v2 137 138 /* --------------------------------------------- 139 * This function provides Neoverse V2- 140 * specific register information for crash 141 * reporting. It needs to return with x6 142 * pointing to a list of register names in ascii 143 * and x8 - x15 having values of registers to be 144 * reported. 145 * --------------------------------------------- 146 */ 147.section .rodata.neoverse_v2_regs, "aS" 148neoverse_v2_regs: /* The ascii list of register names to be reported */ 149 .asciz "cpuectlr_el1", "" 150 151func neoverse_v2_cpu_reg_dump 152 adr x6, neoverse_v2_regs 153 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 154 ret 155endfunc neoverse_v2_cpu_reg_dump 156 157declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 158 neoverse_v2_reset_func, \ 159 neoverse_v2_core_pwr_dwn 160