| f8931606 | 31-Dec-2019 |
Aditya Angadi <aditya.angadi@arm.com> |
drivers/mhu: derive doorbell base address
In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instea
drivers/mhu: derive doorbell base address
In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instead of the MHUV2_BASE_ADDR macro.
Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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| 0a6e7e3b | 24-Oct-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
fconf: Move platform io policies into fconf
Use the firmware configuration framework to store the io_policies
information inside the configuration device tree instead of the static
structure in the
fconf: Move platform io policies into fconf
Use the firmware configuration framework to store the io_policies
information inside the configuration device tree instead of the static
structure in the code base.
The io_policies required by BL1 can't be inside the dtb, as this one is
loaded by BL1, and only available at BL2.
This change currently only applies to FVP platform.
Change-Id: Ic9c1ac3931a4a136aa36f7f58f66d3764c1bfca1
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| 81646055 | 18-Aug-2017 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
plat: marvell: armada: add support for loading MG CM3 images
In order to access MG SRAM, the amb bridge needs to be configured which is
done in bl2 platform init.
For MG CM3, the image is only load
plat: marvell: armada: add support for loading MG CM3 images
In order to access MG SRAM, the amb bridge needs to be configured which is
done in bl2 platform init.
For MG CM3, the image is only loaded to its SRAM and the CM3 itself is
left in reset. It is because the next stage bootloader (e.g. u-boot)
will trigger action which will take it out of reset when needed. This
can happen e.g. when appropriate device-tree setup (which has enabled
802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be
running.
Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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|
| 8c105290 | 23-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.
Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Measured Boot: add function for hash calculation
This patch adds 'calc_hash' function using Mbed TLS library
required for Measured Boot support.
Change-Id: Ifc5aee0162d04db58ec6391e0726a526f29a52bb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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|
| 0581a887 | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
spi: stm32_qspi: Add QSPI support
Add QSPI support (limited to read interface).
Implements the memory map and indirect modes.
Low level driver based on SPI-MEM operations.
Change-Id: Ied698e6de3c17
spi: stm32_qspi: Add QSPI support
Add QSPI support (limited to read interface).
Implements the memory map and indirect modes.
Low level driver based on SPI-MEM operations.
Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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| 695f7df8 | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
fmc: stm32_fmc2_nand: Add FMC2 driver support
Add fmc2_nand driver support. The driver implements
only read interface for NAND devices.
Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522
Signed-o
fmc: stm32_fmc2_nand: Add FMC2 driver support
Add fmc2_nand driver support. The driver implements
only read interface for NAND devices.
Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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| b8718d1f | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
io: stm32image: fix device_size type
Device size could be more than 4GB, we must
define size as unsigned long long.
Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63
Signed-off-by: Lionel Debiev
io: stm32image: fix device_size type
Device size could be more than 4GB, we must
define size as unsigned long long.
Change-Id: I52055cf5c1c15ff18ab9e157aa9b73c8b4fb7b63
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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|
| a13550d0 | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add SPI-NOR framework
SPI-NOR framework is based on SPI-MEM framework using
spi_mem_op execution interface.
It implements read functions and allows NOR configuration
up to quad mode.
Default manage
Add SPI-NOR framework
SPI-NOR framework is based on SPI-MEM framework using
spi_mem_op execution interface.
It implements read functions and allows NOR configuration
up to quad mode.
Default management is 1 data line but it can be overridden
by platform.
It also includes specific quad mode configuration for
Spansion, Micron and Macronix memories.
Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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| c3e57739 | 25-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add SPI-NAND framework
This framework supports SPI-NAND and is based on the
SPI-MEM framework for SPI operations. It uses a common high
level access using the io_mtd.
It is limited to the read func
Add SPI-NAND framework
This framework supports SPI-NAND and is based on the
SPI-MEM framework for SPI operations. It uses a common high
level access using the io_mtd.
It is limited to the read functionalities.
Default behavior is the basic one data line operation
but it could be overridden by platform.
Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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| 05e6a563 | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add SPI-MEM framework
This framework supports SPI operations using a common
spi_mem_op structure:
- command
- addr
- dummy
- data
The framework manages SPI bus configuration:
- speed
- bus wi
Add SPI-MEM framework
This framework supports SPI operations using a common
spi_mem_op structure:
- command
- addr
- dummy
- data
The framework manages SPI bus configuration:
- speed
- bus width (Up to quad mode)
- chip select
Change-Id: Idc2736c59bfc5ac6e55429eba5d385275ea3fbde
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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|
| b114abb6 | 09-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
Add raw NAND framework
The raw NAND framework supports SLC NAND devices.
It introduces a new high level interface (io_mtd) that
defines operations a driver can register to the NAND framework.
This
Add raw NAND framework
The raw NAND framework supports SLC NAND devices.
It introduces a new high level interface (io_mtd) that
defines operations a driver can register to the NAND framework.
This interface will fill in the io_mtd device specification:
- device_size
- erase_size
that could be used by the io_storage interface.
NAND core source file integrates the standard read loop that
performs NAND device read operations using a skip bad block strategy.
A platform buffer must be defined in case of unaligned
data. This buffer must fit to the maximum device page size
defined by PLATFORM_MTD_MAX_PAGE_SIZE.
The raw_nand.c source file embeds the specific NAND operations
to read data.
The read command is a raw page read without any ECC correction.
This can be overridden by a low level driver.
No generic support for write or erase command or software
ECC correction.
NAND ONFI detection is available and can be enabled using
NAND_ONFI_DETECT=1.
For non-ONFI NAND management, platform can define required
information.
Change-Id: Id80e9864456cf47f02b74938cf25d99261da8e82
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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|
| 45cc606e | 17-Jan-2020 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "ld/mtd_framework" into integration
* changes:
io: change seek offset to signed long long
compiler_rt: Import aeabi_ldivmode.S file and dependencies |
| 22c2316d | 14-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "console: 16550: Prepare for skipping initialisation" into integration |
| 70cb0bff | 16-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
io: change seek offset to signed long long
IO seek offset can be set to values above UINT32_MAX, this change
changes the seek offset argument from 'ssize_t' to 'signed long long'.
Fixing platform se
io: change seek offset to signed long long
IO seek offset can be set to values above UINT32_MAX, this change
changes the seek offset argument from 'ssize_t' to 'signed long long'.
Fixing platform seek functions to match the new interface update.
Change-Id: I25de83b3b7abe5f52a7b0fee36f71e60cac9cfcb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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|
| c20c0525 | 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data c
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
L2 accesses
- manage ACP accesses.
Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.
This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT
Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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|
| cd50ffd2 | 12-Dec-2019 |
Andre Przywara <andre.przywara@arm.com> |
console: 16550: Prepare for skipping initialisation
On some platforms the UART might have already been initialised, for
instance by firmware running before TF-A or by a separate management
processor
console: 16550: Prepare for skipping initialisation
On some platforms the UART might have already been initialised, for
instance by firmware running before TF-A or by a separate management
processor. In this case it would not be need to initialise it again
(doing so could create spurious characters). But more importantly this
saves us from knowing the right baudrate and the right base clock rate
for the UART. This can lead to more robust and versatile firmware builds.
Allow to skip the 16550 UART initialisation and baud rate divisor
programming, by interpreting an input clock rate of "0" to signify this
case. This will just skip the call to console_16550_core_init, but still
will register the console properly.
Users should just pass 0 as the second parameter, the baudrate (third
parameter) will then be ignored as well.
Fix copy & paste typos in comments for the console_16550_register()
function on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I9f8fca5b358f878fac0f31dc411358fd160786ee
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|
| 0d35873c | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "allwinner_pmic" into integration
* changes:
allwinner: h6: power: Switch to using the AXP driver
drivers: allwinner: axp: Add AXP805 support |
| 2f3abc19 | 17-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "allwinner_pmic" into integration
* changes:
allwinner: Convert AXP803 regulator setup code into a driver
allwinner: a64: power: Use fdt_for_each_subnode
allwinner: a6
Merge changes from topic "allwinner_pmic" into integration
* changes:
allwinner: Convert AXP803 regulator setup code into a driver
allwinner: a64: power: Use fdt_for_each_subnode
allwinner: a64: power: Remove obsolete register check
allwinner: a64: power: Remove duplicate DT check
allwinner: Build PMIC bus drivers only in BL31
allwinner: a64: power: Make sunxi_turn_off_soc static
allwinner: Merge duplicate code in sunxi_power_down
allwinner: Clean up PMIC-related error handling
allwinner: Synchronize PMIC enumerations
allwinner: Enable clock before resetting I2C/RSB
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|
| 0bc752c9 | 21-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Convert AXP803 regulator setup code into a driver
Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setu
allwinner: Convert AXP803 regulator setup code into a driver
Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.
Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.
I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.
The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
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|
| f6d9c4ca | 21-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
drivers: allwinner: axp: Add AXP805 support
This adds the new regulator list, as well as changes to make the switch
(equivalent to DC1SW on the AXP803) work on both PMICs.
Signed-off-by: Samuel Hol
drivers: allwinner: axp: Add AXP805 support
This adds the new regulator list, as well as changes to make the switch
(equivalent to DC1SW on the AXP803) work on both PMICs.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I9a1eac8ddfc54b27096c10a8eebdd51aaf9b8311
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|
| b8622922 | 15-Sep-2019 |
Gilad Ben-Yossef <gilad.benyossef@arm.com> |
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Chang
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17
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|
| fcc337cf | 16-Sep-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
gic/gic600: add support for multichip configuration
Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to
gic/gic600: add support for multichip configuration
Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to pass their GIC-600 multichip information such as routing table owner,
SPI blocks ownership.
This driver is currently experimental and the driver api may change in
the future.
Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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| 9d811b85 | 08-Oct-2019 |
Yann Gautier <yann.gautier@st.com> |
delay: correct timeout_init_us()
The function has to use read_cntpct_el0() to update the counter, and not
read_cntfrq_el0().
Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7
Signed-off-by: Yann
delay: correct timeout_init_us()
The function has to use read_cntpct_el0() to update the counter, and not
read_cntfrq_el0().
Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 0711ee5c | 24-Sep-2019 |
Lionel Debieve <lionel.debieve@st.com> |
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided mic
delay: timeout detection support
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.
timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.
timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.
Cherry picked from OP-TEE implementation [1].
[1] commit 33d30a74502b ("core: timeout detection support")
Minor:
- Remove stm32mp platform duplicated implementation.
- Add new include in marvell ble.mk
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
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| 19e2af79 | 02-Oct-2019 |
Yann Gautier <yann.gautier@st.com> |
crypto: stm32_hash: align stm32_hash_update() prototype
Use size_t for length parameter in header file, as in .c file.
Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec
Signed-off-by: Yann Gauti
crypto: stm32_hash: align stm32_hash_update() prototype
Use size_t for length parameter in header file, as in .c file.
Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|