refactor(tc): move out platform specific DT binding from tc-base.dtsi

The main purpose of 'tc-base.dtsi' is for common DT bindings, however,
it contains bindings for platform specific.

This patch m

refactor(tc): move out platform specific DT binding from tc-base.dtsi

The main purpose of 'tc-base.dtsi' is for common DT bindings, however,
it contains bindings for platform specific.

This patch moves out these plaform specific bindings to 'tc2.dts' and
'tc3.dts' respectively.

Change-Id: I9355eeff539a3f2940190aef399b4fb4828cbbac
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): move out platform specific code from tc_vers.dtsi

Since now every TC board has its own dts file, this patch moves out the
platform specific code from tc_vers.dtsi to the corresponding

refactor(tc): move out platform specific code from tc_vers.dtsi

Since now every TC board has its own dts file, this patch moves out the
platform specific code from tc_vers.dtsi to the corresponding platform
dts file.

Change-Id: I62e0872eddb2ae18e666a3f8dc0118a539651a9c
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): add platform specific DT files

Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc

refactor(tc): add platform specific DT files

Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc.) are maintained in 'tc_vers.dtsi'.

This patch renames 'tc.dts' to 'tc-base.dtsi' and creates an individual
.dts file for every platform. The purpose is to use 'tc-base.dtsi' for
maintaining common DT binding and every platform's specific definitions
will be moved into its own .dts file. This is a preparation for
sequential refactoring.

It changes to include the header files in platform DTS files but not in
the 'tc-base.dtsi'. This can allow 'tc-base.dtsi' is general enough and
platform DTS files covers platform specific defintions.

Change-Id: I034fb3f8836bcea36e8ad8ae01de41127693b0c6
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'

To follow up the DT naming convention, this patch renames the file
'tc_fvp.dtsi' to 'tc-fvp.dtsi'.

Change-Id: Ib74cc38eb935d3daac87fbab6de4c004b1

refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'

To follow up the DT naming convention, this patch renames the file
'tc_fvp.dtsi' to 'tc-fvp.dtsi'.

Change-Id: Ib74cc38eb935d3daac87fbab6de4c004b1ceddcc
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): introduce a new macro ADDRESSIFY()

Now some macros (e.g., MHU_RX_ADDR(0x), MHU_TX_ADDR(0x), etc) add the
prefix '0x' at the beginning of the addresses for hexadecimal values.

For bett

refactor(tc): introduce a new macro ADDRESSIFY()

Now some macros (e.g., MHU_RX_ADDR(0x), MHU_TX_ADDR(0x), etc) add the
prefix '0x' at the beginning of the addresses for hexadecimal values.

For better readability, this patch introduces a new macro ADDRESSIFY(),
which explictly adds the prefix '0x' for hexadecimal values. With this
new macro, address macros can drop the parameter and be simplified to
hexadecimal address value.

Change-Id: Idd1af0394f6ef8288fbff1fd4d86b1709d1c1d16
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): correlate secure world addresses with platform_def

Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manife

refactor(tc): correlate secure world addresses with platform_def

Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manifest and NS
related entries automatically. Use the macros directly so any changes
can propagate automatically.

The result of this is that TC3 and above get correct secure world
manifests automatically. They were previously broken.

One "breaking" change is that the FWU region moves. This should have
happened previously but it was missed when the secure portion of DRAM
was increased, leaving it in secure memory. This was caught when going
over the definitions and correlating them should prevent this in the
future.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1415e402be8c70f5e22f28eabddcb53298c57a11

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feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't com

feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't come naturally. To avoid this, add the memory node such that it
uses the macros defined in platform_def.

By doing this we can put u-boot out of its misery in trying to come up
with the correct memory node and tf-a's device tree becomes complete.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia92cc6931abb12be2856ac3fb1455e4f3005b326

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feat(tc): add arm_ffa node in dts

For u-boot to use the device tree itself it needs to know about the
arm_ffa module. This is not relevant to linux but it doesn't hurt as it
won't use it.

Signed-of

feat(tc): add arm_ffa node in dts

For u-boot to use the device tree itself it needs to know about the
arm_ffa module. This is not relevant to linux but it doesn't hurt as it
won't use it.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I6e75659e4950c62ce7377dc7941225eb5d7a3d8d

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chore(tc): add dummy entropy to speed up the Linux boot

If the kernel is post 5.19 and is configured with
CONFIG_RANDOM_TRUST_BOOTLOADER=y then entropy can be passed to
Linux via the device tree. Th

chore(tc): add dummy entropy to speed up the Linux boot

If the kernel is post 5.19 and is configured with
CONFIG_RANDOM_TRUST_BOOTLOADER=y then entropy can be passed to
Linux via the device tree. This avoids delaying the Linux boot
waiting for entropy. This is particularly noticeable when
booting android but also speeds up the generation of the ssl
certificates.

Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Change-Id: I4c6136c54f0e971802a2a9de9f88cd32b610dce9

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feat(tc): choose the DPU address and irq based on the target

Currently there are two configurations for DPU
Config 1: Address - 0x2CC0_0000 IRQ - 101
Config 2: Address - 0x40_0000_0000 IRQ - 547

feat(tc): choose the DPU address and irq based on the target

Currently there are two configurations for DPU
Config 1: Address - 0x2CC0_0000 IRQ - 101
Config 2: Address - 0x40_0000_0000 IRQ - 547

Config 1 is used by all FPGA and TC0, TC1 and TC2 FVPs
Config 2 is used by TC3 FVP currently

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: If0097441b6ab90f58911df032e45f6bf06fc7909

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feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU

feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
for DPU and GPU.

These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.

For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1

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refactor(tc): move the FVP RoS to a separate file

In trying to use the same DTS for the FVP and FPGA subvariants we need
to keep track of what is different. Move the FVP RoS, which is different
to t

refactor(tc): move the FVP RoS to a separate file

In trying to use the same DTS for the FVP and FPGA subvariants we need
to keep track of what is different. Move the FVP RoS, which is different
to the FPGA's, to reduce the number of ifdefs and make FVP-only changes
easier.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib7999d3e39de55ab4a30e68dd81f95120be15a8c

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feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The dif

feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
* addresses of GIC and UART
* displays (FPGA uses 4k)
* ethernet devices and SD card (it's non removable on the FPGA)

Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.

Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.

Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13

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feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arran

feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).

Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.

While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.

Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.

In the end, the big/mid/little configurations are:
* TC2 FVP: 1/3/4
* TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
* TC3 both: 2/4/2 (with new capacities)

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b

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feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utili

feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utility space address (needed for MPAM) is different
* no CMN (and therefore cmn-pmu)
* the uart clock is different

This requires the dts to be different between revisions for the first
time. Introduce a tc_vers.dtsi that includes only definitions for things
that are different.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827

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refactor(tc): sanitise the device tree

We have lots of errors in our device tree when running dt-validate.
Remove the majority so that dt-validate-ing is useful now.

Do this by renaming nodes to co

refactor(tc): sanitise the device tree

We have lots of errors in our device tree when running dt-validate.
Remove the majority so that dt-validate-ing is useful now.

Do this by renaming nodes to conform to spec, making addresses lowercase
with no 0x at the front, and removing nodes that shouldn't be there.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1840f0f5de34a56ee240c07eff08d73c856b338e

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feat(tc): add PMU entry

TC has PMUs with interrupts in all cores and Linux needs to be told
about them.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice0e6dab396b90c05f4b9668

feat(tc): add PMU entry

TC has PMUs with interrupts in all cores and Linux needs to be told
about them.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice0e6dab396b90c05f4b9668623ba7b3556a53ac

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chore(tc): remove unused hdlcd

The hdlcd device tree node is not in use for any TC incarnation. The DPU
replaces it. So drop it.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id:

chore(tc): remove unused hdlcd

The hdlcd device tree node is not in use for any TC incarnation. The DPU
replaces it. So drop it.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5393435e36d8307bef909a6519cb40305b77f0cf

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feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total c

feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total compute platform. To make it fit with Op-tee we need to reduce
its available memory.

Also, reserve 4 MB for stmm communication used for firmware update.
The firmware update secure partition and u-boot communicates using the
stmm communication layer and it needs a dedicated memory region.

Co-developed-by: Sergio Alves <sergio.dasilvalves@arm.com>
Co-developed-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0427549845f6c7650b8ef4e450d387fe9702a847

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feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co

feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co-developed-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1f7d7c1c6a5ef67541097ab04670343282458aeb

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fix(tc): correct interrupts

The gic and trbe0 are listed as active high, but the spec says they are
triggered on active low. Correct according to the spec.

While we're at it, convert all interrupts

fix(tc): correct interrupts

The gic and trbe0 are listed as active high, but the spec says they are
triggered on active low. Correct according to the spec.

While we're at it, convert all interrupts to use the macros so hopefully
no such confusion happens again.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2fc01cf0a34b031b95219b9656b613a19a2e9b2a

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feat(tc): interrupt numbers for `smmu_700`

Interrupt numbers definitions and names added to `smmu_700`
node.

Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: Iee0b5e854e5516fce13

feat(tc): interrupt numbers for `smmu_700`

Interrupt numbers definitions and names added to `smmu_700`
node.

Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: Iee0b5e854e5516fce13315c1e6ad5bb2a55246ec

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feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain

The scmi-perf-domain property is a custom property while we
wait for proper support in the kernel for using the scmi_pm_domain
dri

feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain

The scmi-perf-domain property is a custom property while we
wait for proper support in the kernel for using the scmi_pm_domain
driver and scmi_perf_domain driver at the same time.

GPU operating points are now in the SCP firmware.

Change-Id: Ib6d8f52c8bf69194b1d2da4e065a34c4a341c221
Signed-off-by: Ben Horgan <ben.horgan@arm.com>

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refactor(tc): remap console logs

Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP termina

refactor(tc): remap console logs

Remap TF-A console logs from SoC UART2 (S1 terminal) to CSS
secure (UART1_AP terminal) and Linux logs from SoC UART2
(S1 terminal) to CSS non-secure (UART_AP terminal) to align
with the latest FVP TC2 model (version 11.23/17).

Change-Id: I7206e64b65346bfdcc48d6acd3792b436041e45f
Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>

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Merge changes from topic "st-bsec-otp" into integration

* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm

Merge changes from topic "st-bsec-otp" into integration

* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm32mp2): add missing include
feat(st): do not directly call BSEC functions in common code
feat(st): use stm32_get_otp_value_from_idx() in BL31
refactor(st): update test for closed chip
refactor(st-bsec): improve BSEC driver
refactor(st): use dashes for BSEC node names

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