Merge "refactor(tc): neaten platform code after TC2 removal" into integration

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration

* changes:
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
fix(tc): modify ethernet configuration for TC4 FP

Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration

* changes:
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
fix(tc): modify ethernet configuration for TC4 FPGA
fix(tc): modify gpio controller base addr for TC4 FPGA
fix(tc): modify DPU configuration in dts for TC4 FPGA
fix(tc): modify mmc configuration for TC4 FPGA
feat(tc): configure UART for TC4 FPGA

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fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd4899459358299

fix(tc): modify DPU configuration in dts for TC4 FPGA

TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.

Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure acc

Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4

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feat(tc): add MCN PMU nodes in dts for TC4

Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zey

feat(tc): add MCN PMU nodes in dts for TC4

Add MCN PMU nodes in dts for TC4 to use MCN PMU driver in
kernel with perf.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1a85ba646604336ce3f16c28171589af78f65251

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feat(tc): add 'kaslr-seed' node in device tree for TC3

Add 'kaslr-seed' node in device tree for TC3.

Note, TC4 doesn't need to add this node as it can dynamically generate
seed based on CPU arch's

feat(tc): add 'kaslr-seed' node in device tree for TC3

Add 'kaslr-seed' node in device tree for TC3.

Note, TC4 doesn't need to add this node as it can dynamically generate
seed based on CPU arch's RNG_TRAP feature.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I5c3f857d0f4e81ccd3bacb4c1ab032c8ea6e6873

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Merge "feat(tc): add devicetree node for AP/RSE MHU" into integration

Merge changes Ib1b810df,I5492bab5 into integration

* changes:
feat(tc): add dsu pmu node for TC4
feat(tc): enable DSU PMU el1 access for TC4

feat(tc): add devicetree node for AP/RSE MHU

These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.

FPGA doesn't seem to have the MHU instances which are us

feat(tc): add devicetree node for AP/RSE MHU

These dts nodes are used by u-boot MHU/RSE driver to faciliate
communication with RSE over MHU.

FPGA doesn't seem to have the MHU instances which are used to
communicate with RSE so keep rse mhu disabled for fpga.

Signed-off-by: Yu Shihai <yu.shihai@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib10b3da09626e5beb6d6cd87b1618a143234a5d0

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feat(tc): add dsu pmu node for TC4

Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.

Signed-

feat(tc): add dsu pmu node for TC4

Add DSU PMU node for TC4. DSU PMU interrupt is not connected on TC3
but it is connected on IRQ 290 on TC4, so add interrupt property
specifically for TC4.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib1b810df65004987e9f3cf1bbd5deb5d211f3a17

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Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME a

Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME and SME2 options for TC4
feat(tc): add new TC4 RoS definitions
feat(tc): add system generic timer register definition for TC4
feat(tc): allow TARGET_VERSION=4
feat(tc): add MHUv3 register addresses for TC4
feat(tc): add device tree binding for TC4

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feat(tc): update DT for Drage GPU

This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC p

feat(tc): update DT for Drage GPU

This patch incorporates the changes for Drage GPU to uses new access
window interface "IRQ_AW". As the interrupt properties are different
between TC4 and other TC platforms, this patch appends the interrupt
properties in platform specific DT binding file.

Change-Id: I2ca505846f03ce64b8e5f02fd202962dbfe39f25
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3

feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add device tree binding for TC4

Since TC3 and TC4 share most components in the hardware design, they can
reuse the device tree binding. For this reason, this patch extracts the
common modu

feat(tc): add device tree binding for TC4

Since TC3 and TC4 share most components in the hardware design, they can
reuse the device tree binding. For this reason, this patch extracts the
common modules from tc3.dts and put into the file tc3-4-based.dtsi.

As a result, a new created tc4.dts file includes tc3-4-based.dtsi for
support DT binding for the TC4 platform.

Change-Id: Ib7497162cb131d94a722aeaa14a1a37fb0095829
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc):

Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc): change GIC DT property 'interrupt-cells' to 4
feat(tc): add NI-Tower PMU node for TC3
feat(tc): setup ni-tower non-secure access for TC3

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fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signe

fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface

feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface.

Change-Id: Ic7a9d9ce927edbce02c7c09470a009dc56247240
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add PPI partitions in DT binding

Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes fo

feat(tc): add PPI partitions in DT binding

Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes for each microarchitecture type, each with the
property 'affinity' which should be a list of phandles to CPU nodes.

PPI paritions are useful to affine specific PPI with set of CPUs
so that the drivers of micro-architecture specific nodes which uses
PPI can be divided based on CPU list e.g. SPE-PMU, CPU-PMU etc.

Change-Id: If7d47f71387ac982d2d992a0ce2de1652d564bd6
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add NI-Tower PMU node for TC3

Enable NI-Tower PMU on TC3.

Change-Id: I8a4d4e31e84ab33f95bc8b7661e873cf97561b79
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Ya

feat(tc): add NI-Tower PMU node for TC3

Enable NI-Tower PMU on TC3.

Change-Id: I8a4d4e31e84ab33f95bc8b7661e873cf97561b79
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "us_dsu_pmu" into integration

* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for t

Merge changes from topic "us_dsu_pmu" into integration

* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for tc3
feat(tc): enable el1 access to DSU PMU registers
style(tc): remove comment for plat_reset_handler
fix(context-mgmt): keep actlr_el2 value in the init context

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feat(tc): add DSU PMU node for tc3

Add DT binding for Arm DSU PMU node.

Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Le

feat(tc): add DSU PMU node for tc3

Add DT binding for Arm DSU PMU node.

Change-Id: Iadfb5d3bb3f69c7a771516180d1c165e60eef51d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "ip_smmu" into integration

* changes:
feat(tc): bind SMMU-600 with the DPU on TC3 FPGA
feat(tc): bind SMMU-700 with DPU on TC3
refactor(tc): append binding for SMMU-700

Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure acces

Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure access to pmu counters on TC3

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feat(tc): bind SMMU-600 with the DPU on TC3 FPGA

The SMMU 600 is used on TC3 FPGA board with the display device, add the
device tree binding for it.

Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98a

feat(tc): bind SMMU-600 with the DPU on TC3 FPGA

The SMMU 600 is used on TC3 FPGA board with the display device, add the
device tree binding for it.

Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98ae945
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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