1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46040000 /* hex */ 14#define MHU_RX_ADDR 46140000 /* hex */ 15 16#define RSE_MHU_TX_ADDR 49010000 /* hex */ 17#define RSE_MHU_RX_ADDR 49110000 /* hex */ 18 19#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu" 20#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" 21#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" 22 23#define ETHERNET_ADDR 18000000 24#define ETHERNET_INT 109 25 26#define SYS_REGS_ADDR 1c010000 27 28#define MMC_ADDR 1c050000 29#define MMC_INT_0 107 30#define MMC_INT_1 108 31 32#define RTC_ADDR 1c170000 33#define RTC_INT 100 34 35#define KMI_0_ADDR 1c060000 36#define KMI_0_INT 197 37#define KMI_1_ADDR 1c070000 38#define KMI_1_INT 103 39 40#define VIRTIO_BLOCK_ADDR 1c130000 41#define VIRTIO_BLOCK_INT 204 42 43#include "tc-common.dtsi" 44#if TARGET_FLAVOUR_FVP 45#include "tc-fvp.dtsi" 46#else 47#include "tc-fpga.dtsi" 48#endif /* TARGET_FLAVOUR_FVP */ 49#include "tc3-4-base.dtsi" 50 51/ { 52 /* 53 * The kaslr-seed node is a placeholder in DT. In the booting 54 * sequence, it will be initialized in U-Boot and then later 55 * used by Linux kernel. 56 */ 57 chosen { 58 kaslr-seed = <0x0 0x0>; 59 }; 60 61 cs-pmu@0 { 62 compatible = "arm,coresight-pmu"; 63 reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; 64 }; 65 66 cs-pmu@1 { 67 compatible = "arm,coresight-pmu"; 68 reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; 69 }; 70 71 cs-pmu@2 { 72 compatible = "arm,coresight-pmu"; 73 reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; 74 }; 75 76 cs-pmu@3 { 77 compatible = "arm,coresight-pmu"; 78 reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; 79 }; 80 81 spe-pmu-mid { 82 status = "okay"; 83 }; 84 85 spe-pmu-big { 86 status = "okay"; 87 }; 88 89 ni-pmu { 90 compatible = "arm,ni-tower"; 91 reg = <0x0 0x4f000000 0x0 0x4000000>; 92 }; 93 94#if TARGET_FLAVOUR_FVP 95 smmu_700: iommu@3f000000 { 96 status = "okay"; 97 }; 98 99 smmu_700_dpu: iommu@4002a00000 { 100 status = "okay"; 101 }; 102#else 103 smmu_600: smmu@2ce00000 { 104 status = "okay"; 105 }; 106#endif 107 108 dp0: display@DPU_ADDR { 109#if TARGET_FLAVOUR_FVP 110 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 111 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 112#else /* TARGET_FLAVOUR_FPGA */ 113 iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>, 114 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>, 115 <&smmu_600 8>, <&smmu_600 9>; 116#endif 117 }; 118 119 gpu: gpu@2d000000 { 120 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>, 121 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>, 122 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 123 interrupt-names = "JOB", "MMU", "GPU"; 124#if TARGET_FLAVOUR_FVP 125 iommus = <&smmu_700 0x200>; 126#endif 127 }; 128}; 129