1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46040000 /* hex */ 14#define MHU_RX_ADDR 46140000 /* hex */ 15 16#define RSE_MHU_TX_ADDR 49010000 /* hex */ 17#define RSE_MHU_RX_ADDR 49110000 /* hex */ 18 19#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu" 20#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" 21#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" 22 23#define ETHERNET_ADDR 18000000 24#define ETHERNET_INT 109 25 26#define SYS_REGS_ADDR 1c010000 27 28#define MMC_ADDR 1c050000 29#define MMC_INT_0 107 30#define MMC_INT_1 108 31 32#define RTC_ADDR 1c170000 33#define RTC_INT 100 34 35#define KMI_0_ADDR 1c060000 36#define KMI_0_INT 197 37#define KMI_1_ADDR 1c070000 38#define KMI_1_INT 103 39 40#define VIRTIO_BLOCK_ADDR 1c130000 41#define VIRTIO_BLOCK_INT 204 42 43#if TARGET_FLAVOUR_FPGA 44#define DPU_ADDR 2cc00000 45#define DPU_IRQ 69 46#endif 47 48#include "tc-common.dtsi" 49#if TARGET_FLAVOUR_FVP 50#include "tc-fvp.dtsi" 51#else 52#include "tc-fpga.dtsi" 53#endif /* TARGET_FLAVOUR_FVP */ 54#include "tc-base.dtsi" 55 56/ { 57 /* 58 * The kaslr-seed node is a placeholder in DT. In the booting 59 * sequence, it will be initialized in U-Boot and then later 60 * used by Linux kernel. 61 */ 62 chosen { 63 kaslr-seed = <0x0 0x0>; 64 }; 65 66 spe-pmu-mid { 67 status = "okay"; 68 }; 69 70 spe-pmu-big { 71 status = "okay"; 72 }; 73 74 ni-pmu { 75 compatible = "arm,ni-tower"; 76 reg = <0x0 0x4f000000 0x0 0x4000000>; 77 }; 78 79#if TARGET_FLAVOUR_FVP 80 smmu_700: iommu@3f000000 { 81 status = "okay"; 82 }; 83 84 smmu_700_dpu: iommu@4002a00000 { 85 status = "okay"; 86 }; 87#else 88 smmu_600: smmu@2ce00000 { 89 status = "okay"; 90 }; 91#endif 92 93 dp0: display@DPU_ADDR { 94#if TARGET_FLAVOUR_FVP 95 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 96 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 97#else /* TARGET_FLAVOUR_FPGA */ 98 iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>, 99 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>, 100 <&smmu_600 8>, <&smmu_600 9>; 101#endif 102 }; 103 104 gpu: gpu@2d000000 { 105 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>, 106 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>, 107 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 108 interrupt-names = "JOB", "MMU", "GPU"; 109#if TARGET_FLAVOUR_FVP 110 iommus = <&smmu_700 0x200>; 111#endif 112 }; 113}; 114