1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46040000 /* hex */ 14#define MHU_RX_ADDR 46140000 /* hex */ 15 16#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu" 17#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" 18#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" 19 20#define ETHERNET_ADDR 18000000 21#define ETHERNET_INT 109 22 23#define SYS_REGS_ADDR 1c010000 24 25#define MMC_ADDR 1c050000 26#define MMC_INT_0 107 27#define MMC_INT_1 108 28 29#define RTC_ADDR 1c170000 30#define RTC_INT 100 31 32#define KMI_0_ADDR 1c060000 33#define KMI_0_INT 197 34#define KMI_1_ADDR 1c070000 35#define KMI_1_INT 103 36 37#define VIRTIO_BLOCK_ADDR 1c130000 38#define VIRTIO_BLOCK_INT 204 39 40#include "tc-common.dtsi" 41#if TARGET_FLAVOUR_FVP 42#include "tc-fvp.dtsi" 43#else 44#include "tc-fpga.dtsi" 45#endif /* TARGET_FLAVOUR_FVP */ 46#include "tc3-4-base.dtsi" 47 48/ { 49 cs-pmu@0 { 50 compatible = "arm,coresight-pmu"; 51 reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; 52 }; 53 54 cs-pmu@1 { 55 compatible = "arm,coresight-pmu"; 56 reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; 57 }; 58 59 cs-pmu@2 { 60 compatible = "arm,coresight-pmu"; 61 reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; 62 }; 63 64 cs-pmu@3 { 65 compatible = "arm,coresight-pmu"; 66 reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; 67 }; 68 69 spe-pmu-mid { 70 status = "okay"; 71 }; 72 73 spe-pmu-big { 74 status = "okay"; 75 }; 76 77 ni-pmu { 78 compatible = "arm,ni-tower"; 79 reg = <0x0 0x4f000000 0x0 0x4000000>; 80 }; 81 82#if TARGET_FLAVOUR_FVP 83 smmu_700: iommu@3f000000 { 84 status = "okay"; 85 }; 86 87 smmu_700_dpu: iommu@4002a00000 { 88 status = "okay"; 89 }; 90#else 91 smmu_600: smmu@2ce00000 { 92 status = "okay"; 93 }; 94#endif 95 96 dp0: display@DPU_ADDR { 97#if TARGET_FLAVOUR_FVP 98 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 99 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 100#else /* TARGET_FLAVOUR_FPGA */ 101 iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>, 102 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>, 103 <&smmu_600 8>, <&smmu_600 9>; 104#endif 105 }; 106 107 gpu: gpu@2d000000 { 108 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>, 109 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>, 110 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 111 interrupt-names = "JOB", "MMU", "GPU"; 112#if TARGET_FLAVOUR_FVP 113 iommus = <&smmu_700 0x200>; 114#endif 115 }; 116}; 117