1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define MHU_TX_ADDR 46040000 /* hex */ 14#define MHU_RX_ADDR 46140000 /* hex */ 15 16#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu" 17#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu" 18#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu" 19 20#include "tc-common.dtsi" 21#if TARGET_FLAVOUR_FVP 22#include "tc-fvp.dtsi" 23#else 24#include "tc-fpga.dtsi" 25#endif /* TARGET_FLAVOUR_FVP */ 26#include "tc3-4-base.dtsi" 27 28/ { 29 cs-pmu@0 { 30 compatible = "arm,coresight-pmu"; 31 reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>; 32 }; 33 34 cs-pmu@1 { 35 compatible = "arm,coresight-pmu"; 36 reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>; 37 }; 38 39 cs-pmu@2 { 40 compatible = "arm,coresight-pmu"; 41 reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>; 42 }; 43 44 cs-pmu@3 { 45 compatible = "arm,coresight-pmu"; 46 reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>; 47 }; 48 49 spe-pmu-mid { 50 status = "okay"; 51 }; 52 53 spe-pmu-big { 54 status = "okay"; 55 }; 56 57 dsu-pmu { 58 compatible = "arm,dsu-pmu"; 59 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; 60 }; 61 62 ni-pmu { 63 compatible = "arm,ni-tower"; 64 reg = <0x0 0x4f000000 0x0 0x4000000>; 65 }; 66 67#if TARGET_FLAVOUR_FVP 68 smmu_700: iommu@3f000000 { 69 status = "okay"; 70 }; 71 72 smmu_700_dpu: iommu@4002a00000 { 73 status = "okay"; 74 }; 75#else 76 smmu_600: smmu@2ce00000 { 77 status = "okay"; 78 }; 79#endif 80 81 dp0: display@DPU_ADDR { 82#if TARGET_FLAVOUR_FVP 83 iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, 84 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; 85#else /* TARGET_FLAVOUR_FPGA */ 86 iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>, 87 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>, 88 <&smmu_600 8>, <&smmu_600 9>; 89#endif 90 }; 91 92 gpu: gpu@2d000000 { 93#if TARGET_FLAVOUR_FVP 94 iommus = <&smmu_700 0x200>; 95#endif 96 }; 97}; 98