rcar_gen3: drivers: watchdog

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: serial controller interface

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: spi multio bus controller

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: rom api

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: power controller

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: console

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: io [emmc/mem]

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: i2c dvfs

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: emmc

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: dma

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: micro delay generator

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: cpld

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: board identification

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: avs [adaptive voltage scaling]

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: authentication

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: staging

- ddr
- pfc [pin function controller]
- qos [bandwidth]

checkpatch.pl is generating too many errors.

rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author

rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date: Thu Aug 30 21:26:41 2018 +0900
Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
git@github.com:ARMmbed/mbedtls.git [devel]

Merge: 68dbc94 f34a4c1
Author: Simon Butcher <simon.butcher@arm.com>
Date: Thu Aug 30 00:57:28 2018 +0100

* optee_os:
https://github.com/BayLibre/optee_os

Until it gets merged into OP-TEE, the port requires Renesas' Trusted
Environment with a modification to support power management.

Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
Date: Thu Aug 30 16:49:49 2018 +0200
plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
The port has beent tested using mainline uboot.

Author: Fabio Estevam <festevam@gmail.com>
Date: Tue Sep 4 10:23:12 2018 -0300

*linux:
The port has beent tested using mainline kernel.

Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Sep 16 11:52:37 2018 -0700
Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
-------
enable kernel's cpuidle arm_idle driver and boot

* system suspend
--------------
$ cat suspend.sh
#!/bin/bash
i2cset -f -y 7 0x30 0x20 0x0F
read -p "Switch off SW23 and press return " foo
echo mem > /sys/power/state

* cpu hotplug:
------------
$ cat offline.sh
#!/bin/bash
nbr=$1
echo 0 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

$ cat online.sh
#!/bin/bash
nbr=$1
echo 1 > /sys/devices/system/cpu/cpu$nbr/online
printf "ONLINE: " && cat /sys/devices/system/cpu/online
printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>

show more ...

stm32mp1: add an IO to read MMC devices

Whereas the GPT table is read with io_block, the binaries to be loaded
(e.g. BL33) cannot use it, as it is not suitable to read them block by
block, or the bo

stm32mp1: add an IO to read MMC devices

Whereas the GPT table is read with io_block, the binaries to be loaded
(e.g. BL33) cannot use it, as it is not suitable to read them block by
block, or the boot time would be very bad.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

stm32mp1: add an IO to read STM32IMAGE binaries

This IO is required to read binaries with STM32 header.
This header is added with the stm32image tool.

Signed-off-by: Yann Gautier <yann.gautier@st.c

stm32mp1: add an IO to read STM32IMAGE binaries

This IO is required to read binaries with STM32 header.
This header is added with the stm32image tool.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

stm32mp1: add sdmmc2 driver

This driver is for the STMicroelectronics sdmmc2 IP
which is in STM32MP1 SoC.
It uses the MMC framework, and can address either eMMC or SD-card.

Signed-off-by: Yann Gaut

stm32mp1: add sdmmc2 driver

This driver is for the STMicroelectronics sdmmc2 IP
which is in STM32MP1 SoC.
It uses the MMC framework, and can address either eMMC or SD-card.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

Merge pull request #1626 from Yann-lms/partition_verbose

drivers: partition: correct compilation error in VERBOSE mode

Merge pull request #1630 from antonio-nino-diaz-arm/an/fix-console

pl011: cnds: cbmem: 16550: Fix comments

pl011: cnds: cbmem: 16550: Fix comments

The comments with the prototypes of the register functions of the
console drivers are incorrect. The arguments are wrong. This patch fixes
them.

Change-Id: I

pl011: cnds: cbmem: 16550: Fix comments

The comments with the prototypes of the register functions of the
console drivers are incorrect. The arguments are wrong. This patch fixes
them.

Change-Id: I38c4b481ee69e840780111c42f03c0752eb6315c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

show more ...

Merge pull request #1622 from bryanodonoghue/master+imx7-mmc_fix

drivers: imx: mxc_usdhc: Do not set MMC_RSP_48 for MMC_RESPONSE_R2

drivers: partition: correct compilation error in VERBOSE mode

Signed-off-by: Yann Gautier <yann.gautier@st.com>