| 3333d2ca | 15-Oct-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: drivers: ddr: Move DDR drivers out of staging
Now that DDR drivers are mostly cleaned up , move them out of staging.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id:
rcar_gen3: drivers: ddr: Move DDR drivers out of staging
Now that DDR drivers are mostly cleaned up , move them out of staging.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9de63f847a0ef9ac27a79fb0f848c351fd7f4da6
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| c20c0525 | 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data c
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
L2 accesses
- manage ACP accesses.
Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.
This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT
Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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| cd50ffd2 | 12-Dec-2019 |
Andre Przywara <andre.przywara@arm.com> |
console: 16550: Prepare for skipping initialisation
On some platforms the UART might have already been initialised, for
instance by firmware running before TF-A or by a separate management
processor
console: 16550: Prepare for skipping initialisation
On some platforms the UART might have already been initialised, for
instance by firmware running before TF-A or by a separate management
processor. In this case it would not be need to initialise it again
(doing so could create spurious characters). But more importantly this
saves us from knowing the right baudrate and the right base clock rate
for the UART. This can lead to more robust and versatile firmware builds.
Allow to skip the 16550 UART initialisation and baud rate divisor
programming, by interpreting an input clock rate of "0" to signify this
case. This will just skip the call to console_16550_core_init, but still
will register the console properly.
Users should just pass 0 as the second parameter, the baudrate (third
parameter) will then be ignored as well.
Fix copy & paste typos in comments for the console_16550_register()
function on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I9f8fca5b358f878fac0f31dc411358fd160786ee
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| 31645dde | 18-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "drivers: marvell: comphy-a3700: support SGMII COMPHY power off" into integration |
| 90a76bab | 18-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2" into integration |
| 0d35873c | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "allwinner_pmic" into integration
* changes:
allwinner: h6: power: Switch to using the AXP driver
drivers: allwinner: axp: Add AXP805 support |
| 2f3abc19 | 17-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "allwinner_pmic" into integration
* changes:
allwinner: Convert AXP803 regulator setup code into a driver
allwinner: a64: power: Use fdt_for_each_subnode
allwinner: a6
Merge changes from topic "allwinner_pmic" into integration
* changes:
allwinner: Convert AXP803 regulator setup code into a driver
allwinner: a64: power: Use fdt_for_each_subnode
allwinner: a64: power: Remove obsolete register check
allwinner: a64: power: Remove duplicate DT check
allwinner: Build PMIC bus drivers only in BL31
allwinner: a64: power: Make sunxi_turn_off_soc static
allwinner: Merge duplicate code in sunxi_power_down
allwinner: Clean up PMIC-related error handling
allwinner: Synchronize PMIC enumerations
allwinner: Enable clock before resetting I2C/RSB
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| 186acdd9 | 16-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "cryptocell: add cryptocell 712 RSA 3K support" into integration |
| 0bc752c9 | 21-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Convert AXP803 regulator setup code into a driver
Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setu
allwinner: Convert AXP803 regulator setup code into a driver
Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.
Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.
I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.
The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
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| f6d9c4ca | 21-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
drivers: allwinner: axp: Add AXP805 support
This adds the new regulator list, as well as changes to make the switch
(equivalent to DC1SW on the AXP803) work on both PMICs.
Signed-off-by: Samuel Hol
drivers: allwinner: axp: Add AXP805 support
This adds the new regulator list, as well as changes to make the switch
(equivalent to DC1SW on the AXP803) work on both PMICs.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I9a1eac8ddfc54b27096c10a8eebdd51aaf9b8311
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| 629dd61f | 05-Nov-2019 |
Marek Behún <marek.behun@nic.cz> |
drivers: marvell: comphy-a3700: support SGMII COMPHY power off
Add support for powering off the SGMII COMPHY (on lanes 0 and 1).
This is needed sometimes on Turris Mox when using KEXEC.
There is al
drivers: marvell: comphy-a3700: support SGMII COMPHY power off
Add support for powering off the SGMII COMPHY (on lanes 0 and 1).
This is needed sometimes on Turris Mox when using KEXEC.
There is also another benefit of a little energy saving when the given
network interface is down.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I55ae0fe3627e7cc0f65c78a00771939d8bf5399f
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| b662232d | 08-Oct-2019 |
Marek Behún <marek.behun@nic.cz> |
drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2
When USB3 is on lane 2 and indirect register access is used, the polling
at the end of the mvebu_a3700_comphy_usb3_power_on functi
drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2
When USB3 is on lane 2 and indirect register access is used, the polling
at the end of the mvebu_a3700_comphy_usb3_power_on function is
incorrect.
The LOOPBACK_REG0 register should not be used at all. Instead we have to
write the LANE_STATUS1 register address (with offset
USB3PHY_LANE2_REG_BASE_OFFSET) into the indirect address register and
then we should poll indirect data register.
This fixes problems on Turris Mox, which uses lane 2 for USB3.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I968b0cccee5ddbe10a2b5614e52e52d87682aacd
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| b8622922 | 15-Sep-2019 |
Gilad Ben-Yossef <gilad.benyossef@arm.com> |
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Chang
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17
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| ade3f5df | 06-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "bs/libc" into integration
* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AAr
Merge changes from topic "bs/libc" into integration
* changes:
libc: Consolidate the size_t and NULL definitions
libc: Consolidate unified definitions
libc: Unify intmax_t and uintmax_t on AArch32/64
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| b382ac68 | 25-Oct-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
libc: Consolidate unified definitions
As supporting architectures aside from AArch32 and AArch64 is not a
concern, keeping identical definitions in two places for a large part
of the libc seems coun
libc: Consolidate unified definitions
As supporting architectures aside from AArch32 and AArch64 is not a
concern, keeping identical definitions in two places for a large part
of the libc seems counterproductive
The int128 types were left un-unified as __int128 is not supported by
gcc on AArch32
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf
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| 87b582ef | 03-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Enable -Wlogical-op always" into integration |
| f67a2977 | 03-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Enable -Wshadow always" into integration |
| d7b4cd41 | 18-Sep-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Enable -Wlogical-op always
-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While t
Enable -Wlogical-op always
-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While these are perfectly valid behavior, they
can be a sign that something is slightly off.
This patch adds this warning to gcc and it's closest equivalent to
clang, while also fixing any warnings that enabling them causes.
Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| b7f6525d | 17-Sep-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Enable -Wshadow always
Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion
Enable -Wshadow always
Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion and can make refactoring and bug hunting
more difficult.
This patch moves -Wshadow from WARNING2 into the general warning group
so it is always used. It also fixes all warnings that this introduces
by simply renaming the local variable to a new name
Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| ac426351 | 19-Nov-2019 |
Max Shvetsov <maksims.svecovs@arm.com> |
GIC-600: Fix include ordering according to the coding style
Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> |
| 7a7fbb12 | 31-Jul-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
GIC-600: Fix power up sequence
Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Section 3.6.1 in the GIC-600 TRM describes
the pow
GIC-600: Fix power up sequence
Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Section 3.6.1 in the GIC-600 TRM describes
the power-up and power-down sequence in pseudo code,
which deviates from the current TF-A implementation
in drivers/arm/gic/v3/gic600.c.
For powering on a redistributor, the pseudo code suggests
to loop over the whole sequence (check for transition,
write request bit) instead of just looping over the
ready bit read as TF-A does in gic600_pwr_on().
This patch fixes GIC-600 power up sequence according
to the TRM.
Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| 90199457 | 14-Nov-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "TF-A: Fix non-standard frequency issue in udelay" into integration |
| f2976bdd | 31-Oct-2019 |
Max Shvetsov <maksims.svecovs@arm.com> |
TF-A: Fix non-standard frequency issue in udelay
Previous implementation of timers assumed that clk_div has pretty
representation in MHz (10MHz, 100MHz, etc). Unusual frequencies
(99.99MHz) were cau
TF-A: Fix non-standard frequency issue in udelay
Previous implementation of timers assumed that clk_div has pretty
representation in MHz (10MHz, 100MHz, etc). Unusual frequencies
(99.99MHz) were causing assertion error and made udelay unusable.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic915fff224369d113fd9f8edbcfff169fca8beac
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| 415f67e3 | 12-Nov-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes from topic "gic600_multichip" into integration
* changes:
gic/gic600: add support for multichip configuration
plat/arm/gicv3: add support for probing multiple GIC Redistributor fra
Merge changes from topic "gic600_multichip" into integration
* changes:
gic/gic600: add support for multichip configuration
plat/arm/gicv3: add support for probing multiple GIC Redistributor frames
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| fcc337cf | 16-Sep-2019 |
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> |
gic/gic600: add support for multichip configuration
Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to
gic/gic600: add support for multichip configuration
Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to pass their GIC-600 multichip information such as routing table owner,
SPI blocks ownership.
This driver is currently experimental and the driver api may change in
the future.
Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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