Merge changes from topic "bk/errata_refactor" into integration

* changes:
feat(cpus): add more errata framework helpers
docs: document the errata framework

fix(cpus): reduce generic_errata_report()'s size

For a pretty implementation and straightforward code, the CVE/erratum
dispatching of the errata status reporting was done with a macro,
closely follo

fix(cpus): reduce generic_errata_report()'s size

For a pretty implementation and straightforward code, the CVE/erratum
dispatching of the errata status reporting was done with a macro,
closely following the old code. Unfortunately, this produces a function
that was over a kilobyte in size, which unsurprisingly doesn't fit on
some platforms.

Convert the macro to a proper C function and call it once. Also hide the
errata ordering checking behind the FEATURE_DETECTION flag to further
save space. This functionality is not necessary for most builds.
Development and platform bringup builds, which should find this
functionality useful, are expected to have FEATURE_DETECTION enabled.

This reduces the function to under 600 bytes.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibf5376a26cbae28d9dc010128452cb3c694a3f78

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docs: document the errata framework

Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan

docs: document the errata framework

Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idd876d8e598b5dfe1193aa3e7375c52f6edf5671

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Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration

docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017a

docs: update PSCI reference

PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017af4d51f6d063a7501b27e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "docs: update Measured Boot PoC" into integration

Merge "chore(bl): add UNALIGNED symbols for TEXT/RODATA" into integration

Merge changes from topics "hm/latex", "hm/latexpdf" into integration

* changes:
fix(docs): fix build errors for latexpdf
chore: reformat sphinx configuration

chore(bl): add UNALIGNED symbols for TEXT/RODATA

Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the l

chore(bl): add UNALIGNED symbols for TEXT/RODATA

Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the linker scripts") for
RO_END/COHERENT_RAM. These symbols help to know how much free
space is in the final binary because of page alignment.

Also show all *UNALIGNED__ symbols via poetry.
For example:
poetry run memory -p zynqmp -b debug

Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(docs): fix build errors for latexpdf

Fixes errors encountered when handling SVG graphics, unicode characters,
and deeply nested lists (i.e. in the change log) with the `latexpdf`
docs build. Add

fix(docs): fix build errors for latexpdf

Fixes errors encountered when handling SVG graphics, unicode characters,
and deeply nested lists (i.e. in the change log) with the `latexpdf`
docs build. Adds `sphinxcontrib-svg2pdfconverter` to allow embedding SVG
images into PDF files; changes the LaTeX engine to XeLaTex to provide
wider support for unicode characters (see [1] for more details); and
increases the maximum list depth.

[1] https://www.sphinx-doc.org/en/master/usage/configuration.html#confval-latex_engine

Change-Id: I2ee265d301f6822bae7aa6dfa3a8bfcf070076d3
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update p

Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update pwr_domain_suspend

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docs: update Measured Boot PoC

Updated the Measured Boot PoC to be compliant with the current TF-A
implementation that supports multiple Measured Boot backends, which
are the RSS and Event Log.

Cha

docs: update Measured Boot PoC

Updated the Measured Boot PoC to be compliant with the current TF-A
implementation that supports multiple Measured Boot backends, which
are the RSS and Event Log.

Change-Id: I8a38a801dd75e6282d103e154966959bba2d1ec7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the doc

feat(ast2700): add Aspeed AST2700 platform support

Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.

Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

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Merge "docs: add detail to assembly language guideline" into integration

Merge "fix(doc): match boot-order size to implementation" into integration

Merge changes from topic "hm/memmap-feat" into integration

* changes:
feat(memmap): add topological memory view
feat(memmap): add tabular memory use data

Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control regist

Merge changes from topic "bk/clearups" into integration

* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control register setup section
chore(pauth): remove redundant pauth_disable_el3() call

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chore(fconf): rename last occurences of set_fw_config_info()

set_fw_config_info() interface got renamed into set_config_info() as
part of commit f441718936a6b72583d03eebf8057bbf29446989 ("lib/fconf:

chore(fconf): rename last occurences of set_fw_config_info()

set_fw_config_info() interface got renamed into set_config_info() as
part of commit f441718936a6b72583d03eebf8057bbf29446989 ("lib/fconf:
Update 'set_fw_config_info' function"). Rename a few left-overs of the
old name.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I119719cd7f3ba544e0c4c438e5341d35c7b5bdc2

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docs: add detail to assembly language guideline

Assembly language is rarely required and when it is, there are a lot of
helpers available to reduce the amount needed. Update the guidelines to
give p

docs: add detail to assembly language guideline

Assembly language is rarely required and when it is, there are a lot of
helpers available to reduce the amount needed. Update the guidelines to
give pointers to them.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic484e4ba57242594c351a9185ecb625d6e5dc223

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chore: reformat sphinx configuration

Format the configuration file to follow our coding guidelines and common
Python style conventions.

Change-Id: Ic83372287db08df0662f562f7683a02ddff0bac8
Signed-o

chore: reformat sphinx configuration

Format the configuration file to follow our coding guidelines and common
Python style conventions.

Change-Id: Ic83372287db08df0662f562f7683a02ddff0bac8
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "hm/memmap-feat" into integration

* changes:
build(bl32): add symbols for memory layout
build(bl31): add symbols for memory layout
build(bl2): add symbols for memory l

Merge changes from topic "hm/memmap-feat" into integration

* changes:
build(bl32): add symbols for memory layout
build(bl31): add symbols for memory layout
build(bl2): add symbols for memory layout
build(bl1): add symbols for memory layout
refactor: improve readability of symbol table

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docs: clarify maintainers election process

Add a new page in TF-A documentation for clarifying the process to
elect a new maintainer. This builds on top of the Trusted Firmware
process [1], with the

docs: clarify maintainers election process

Add a new page in TF-A documentation for clarifying the process to
elect a new maintainer. This builds on top of the Trusted Firmware
process [1], with the following TF-A specific details:

- Must have contributed to the project for at least a couple of years.
- Must dedicate at least 2 hours a week for maintainer duties.
- Details about the election process. In particular, setting a
one-calendar-week deadline for other maintainers to raise
objections.

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ibef08bbbd4d18cd7aea13e01ba570972a7ee808d

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docs: consolidate code review process documentation

From the page listing the maintainers and code owners [1], add a link
to the code review guidelines page [2], which in turn has a link to
the tf.o

docs: consolidate code review process documentation

From the page listing the maintainers and code owners [1], add a link
to the code review guidelines page [2], which in turn has a link to
the tf.org code review process [3].

Before that patch, both pages [1] and [2] had a link to
[3]. Hopefully, this change will guide the reader better so they don't
miss out on any information.

Additionally, move some of the information from the top of page [1]
into page [2] and add extra details about the code review process used
in TF-A and how that get translated in Gerrit.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/about/maintainers.html
[2] https://trustedfirmware-a.readthedocs.io/en/latest/process/code-review-guidelines.html
[3] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I56562a72443f03fff16077dadc411ef4ee78666d

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fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t

This patch adds a new optional member `pwr_domain_validate_suspend` to
the `plat_psci_ops_t` structure that allows a platform t

fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t

This patch adds a new optional member `pwr_domain_validate_suspend` to
the `plat_psci_ops_t` structure that allows a platform to optionally
perform platform specific validations in OS-initiated mode. This is
conditionally compiled into the build depending on the value of the
`PSCI_OS_INIT_MODE` build option.

In https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17682,
the return type of the `pwr_domain_suspend` handler was updated from
`void` to `int` to allow a platform to optionally perform platform
specific validations in OS-initiated mode. However, when an error code
other than `PSCI_E_SUCCESS` is returned, the current exit path does not
undo the operations in `psci_suspend_to_pwrdown_start`, and as a result,
the system ends up in an unexpected state.

The fix in this patch prevents the need to undo the operations in
`psci_suspend_to_pwrdown_start`, by allowing the platform to first
perform any necessary platform specific validations before the PSCI
generic code proceeds to the point of no return where the CPU_SUSPEND
request is expected to complete successfully.

Change-Id: I05d92c7ea3f5364da09af630d44d78252185db20
Signed-off-by: Wing Li <wingers@google.com>

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Merge "docs: fix syntax error in note" into integration