1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 139 140 /* 141 * Initialize EL1 context registers unless SPMC is running 142 * at S-EL2. 143 */ 144 #if !SPMD_SPM_AT_SEL2 145 setup_el1_context(ctx, ep); 146 #endif 147 148 manage_extensions_secure(ctx); 149 } 150 151 #if ENABLE_RME 152 /****************************************************************************** 153 * This function performs initializations that are specific to REALM state 154 * and updates the cpu context specified by 'ctx'. 155 *****************************************************************************/ 156 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 157 { 158 u_register_t scr_el3; 159 el3_state_t *state; 160 161 state = get_el3state_ctx(ctx); 162 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 163 164 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 165 166 if (is_feat_csv2_2_supported()) { 167 /* Enable access to the SCXTNUM_ELx registers. */ 168 scr_el3 |= SCR_EnSCXT_BIT; 169 } 170 171 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 172 } 173 #endif /* ENABLE_RME */ 174 175 /****************************************************************************** 176 * This function performs initializations that are specific to NON-SECURE state 177 * and updates the cpu context specified by 'ctx'. 178 *****************************************************************************/ 179 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 180 { 181 u_register_t scr_el3; 182 el3_state_t *state; 183 184 state = get_el3state_ctx(ctx); 185 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 186 187 /* SCR_NS: Set the NS bit */ 188 scr_el3 |= SCR_NS_BIT; 189 190 /* Allow access to Allocation Tags when MTE is implemented. */ 191 scr_el3 |= SCR_ATA_BIT; 192 193 #if !CTX_INCLUDE_PAUTH_REGS 194 /* 195 * Pointer Authentication feature, if present, is always enabled by default 196 * for Non secure lower exception levels. We do not have an explicit 197 * flag to set it. 198 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 199 * exception levels of secure and realm worlds. 200 * 201 * To prevent the leakage between the worlds during world switch, 202 * we enable it only for the non-secure world. 203 * 204 * If the Secure/realm world wants to use pointer authentication, 205 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 206 * it will be enabled globally for all the contexts. 207 * 208 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 209 * other than EL3 210 * 211 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 212 * than EL3 213 */ 214 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 215 216 #endif /* CTX_INCLUDE_PAUTH_REGS */ 217 218 #if HANDLE_EA_EL3_FIRST_NS 219 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 220 scr_el3 |= SCR_EA_BIT; 221 #endif 222 223 #if RAS_TRAP_NS_ERR_REC_ACCESS 224 /* 225 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 226 * and RAS ERX registers from EL1 and EL2(from any security state) 227 * are trapped to EL3. 228 * Set here to trap only for NS EL1/EL2 229 * 230 */ 231 scr_el3 |= SCR_TERR_BIT; 232 #endif 233 234 if (is_feat_csv2_2_supported()) { 235 /* Enable access to the SCXTNUM_ELx registers. */ 236 scr_el3 |= SCR_EnSCXT_BIT; 237 } 238 239 #ifdef IMAGE_BL31 240 /* 241 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 242 * indicated by the interrupt routing model for BL31. 243 */ 244 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 245 #endif 246 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 247 248 /* Initialize EL1 context registers */ 249 setup_el1_context(ctx, ep); 250 251 /* Initialize EL2 context registers */ 252 #if CTX_INCLUDE_EL2_REGS 253 254 /* 255 * Initialize SCTLR_EL2 context register using Endianness value 256 * taken from the entrypoint attribute. 257 */ 258 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 259 sctlr_el2 |= SCTLR_EL2_RES1; 260 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 261 sctlr_el2); 262 263 if (is_feat_hcx_supported()) { 264 /* 265 * Initialize register HCRX_EL2 with its init value. 266 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 267 * chance that this can lead to unexpected behavior in lower 268 * ELs that have not been updated since the introduction of 269 * this feature if not properly initialized, especially when 270 * it comes to those bits that enable/disable traps. 271 */ 272 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 273 HCRX_EL2_INIT_VAL); 274 } 275 276 if (is_feat_fgt_supported()) { 277 /* 278 * Initialize HFG*_EL2 registers with a default value so legacy 279 * systems unaware of FEAT_FGT do not get trapped due to their lack 280 * of initialization for this feature. 281 */ 282 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 283 HFGITR_EL2_INIT_VAL); 284 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 285 HFGRTR_EL2_INIT_VAL); 286 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 287 HFGWTR_EL2_INIT_VAL); 288 } 289 #endif /* CTX_INCLUDE_EL2_REGS */ 290 291 manage_extensions_nonsecure(ctx); 292 } 293 294 /******************************************************************************* 295 * The following function performs initialization of the cpu_context 'ctx' 296 * for first use that is common to all security states, and sets the 297 * initial entrypoint state as specified by the entry_point_info structure. 298 * 299 * The EE and ST attributes are used to configure the endianness and secure 300 * timer availability for the new execution context. 301 ******************************************************************************/ 302 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 303 { 304 u_register_t cptr_el3; 305 u_register_t scr_el3; 306 el3_state_t *state; 307 gp_regs_t *gp_regs; 308 309 state = get_el3state_ctx(ctx); 310 311 /* Clear any residual register values from the context */ 312 zeromem(ctx, sizeof(*ctx)); 313 314 /* 315 * The lower-EL context is zeroed so that no stale values leak to a world. 316 * It is assumed that an all-zero lower-EL context is good enough for it 317 * to boot correctly. However, there are very few registers where this 318 * is not true and some values need to be recreated. 319 */ 320 #if CTX_INCLUDE_EL2_REGS 321 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 322 323 /* 324 * These bits are set in the gicv3 driver. Losing them (especially the 325 * SRE bit) is problematic for all worlds. Henceforth recreate them. 326 */ 327 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 328 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 329 write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2); 330 #endif /* CTX_INCLUDE_EL2_REGS */ 331 332 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 333 scr_el3 = SCR_RESET_VAL; 334 335 /* 336 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 337 * EL2, EL1 and EL0 are not trapped to EL3. 338 * 339 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 340 * EL2, EL1 and EL0 are not trapped to EL3. 341 * 342 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 343 * both Security states and both Execution states. 344 * 345 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 346 * Non-secure memory. 347 */ 348 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 349 350 scr_el3 |= SCR_SIF_BIT; 351 352 /* 353 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 354 * Exception level as specified by SPSR. 355 */ 356 if (GET_RW(ep->spsr) == MODE_RW_64) { 357 scr_el3 |= SCR_RW_BIT; 358 } 359 360 /* 361 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 362 * Secure timer registers to EL3, from AArch64 state only, if specified 363 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 364 * bit always behaves as 1 (i.e. secure physical timer register access 365 * is not trapped) 366 */ 367 if (EP_GET_ST(ep->h.attr) != 0U) { 368 scr_el3 |= SCR_ST_BIT; 369 } 370 371 /* 372 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 373 * SCR_EL3.HXEn. 374 */ 375 if (is_feat_hcx_supported()) { 376 scr_el3 |= SCR_HXEn_BIT; 377 } 378 379 /* 380 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 381 * registers are trapped to EL3. 382 */ 383 #if ENABLE_FEAT_RNG_TRAP 384 scr_el3 |= SCR_TRNDR_BIT; 385 #endif 386 387 #if FAULT_INJECTION_SUPPORT 388 /* Enable fault injection from lower ELs */ 389 scr_el3 |= SCR_FIEN_BIT; 390 #endif 391 392 #if CTX_INCLUDE_PAUTH_REGS 393 /* 394 * Enable Pointer Authentication globally for all the worlds. 395 * 396 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 397 * other than EL3 398 * 399 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 400 * than EL3 401 */ 402 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 403 #endif /* CTX_INCLUDE_PAUTH_REGS */ 404 405 /* 406 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 407 */ 408 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 409 scr_el3 |= SCR_TCR2EN_BIT; 410 } 411 412 /* 413 * SCR_EL3.PIEN: Enable permission indirection and overlay 414 * registers for AArch64 if present. 415 */ 416 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 417 scr_el3 |= SCR_PIEN_BIT; 418 } 419 420 /* 421 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 422 */ 423 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 424 scr_el3 |= SCR_GCSEn_BIT; 425 } 426 427 /* 428 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 429 * All fields are architecturally UNKNOWN on reset. 430 * 431 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 432 * by Advanced SIMD, floating-point or SVE instructions (if 433 * implemented) do not trap to EL3. 434 * 435 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 436 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 437 */ 438 cptr_el3 = CPTR_EL3_RESET_VAL & ~(TFP_BIT | TCPAC_BIT); 439 440 write_ctx_reg(state, CTX_CPTR_EL3, cptr_el3); 441 442 /* 443 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 444 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 445 * next mode is Hyp. 446 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 447 * same conditions as HVC instructions and when the processor supports 448 * ARMv8.6-FGT. 449 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 450 * CNTPOFF_EL2 register under the same conditions as HVC instructions 451 * and when the processor supports ECV. 452 */ 453 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 454 || ((GET_RW(ep->spsr) != MODE_RW_64) 455 && (GET_M32(ep->spsr) == MODE32_hyp))) { 456 scr_el3 |= SCR_HCE_BIT; 457 458 if (is_feat_fgt_supported()) { 459 scr_el3 |= SCR_FGTEN_BIT; 460 } 461 462 if (is_feat_ecv_supported()) { 463 scr_el3 |= SCR_ECVEN_BIT; 464 } 465 } 466 467 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 468 if (is_feat_twed_supported()) { 469 /* Set delay in SCR_EL3 */ 470 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 471 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 472 << SCR_TWEDEL_SHIFT); 473 474 /* Enable WFE delay */ 475 scr_el3 |= SCR_TWEDEn_BIT; 476 } 477 478 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 479 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 480 if (is_feat_sel2_supported()) { 481 scr_el3 |= SCR_EEL2_BIT; 482 } 483 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 484 485 /* 486 * Populate EL3 state so that we've the right context 487 * before doing ERET 488 */ 489 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 490 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 491 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 492 493 /* 494 * Store the X0-X7 value from the entrypoint into the context 495 * Use memcpy as we are in control of the layout of the structures 496 */ 497 gp_regs = get_gpregs_ctx(ctx); 498 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 499 } 500 501 /******************************************************************************* 502 * Context management library initialization routine. This library is used by 503 * runtime services to share pointers to 'cpu_context' structures for secure 504 * non-secure and realm states. Management of the structures and their associated 505 * memory is not done by the context management library e.g. the PSCI service 506 * manages the cpu context used for entry from and exit to the non-secure state. 507 * The Secure payload dispatcher service manages the context(s) corresponding to 508 * the secure state. It also uses this library to get access to the non-secure 509 * state cpu context pointers. 510 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 511 * which will be used for programming an entry into a lower EL. The same context 512 * will be used to save state upon exception entry from that EL. 513 ******************************************************************************/ 514 void __init cm_init(void) 515 { 516 /* 517 * The context management library has only global data to initialize, but 518 * that will be done when the BSS is zeroed out. 519 */ 520 } 521 522 /******************************************************************************* 523 * This is the high-level function used to initialize the cpu_context 'ctx' for 524 * first use. It performs initializations that are common to all security states 525 * and initializations specific to the security state specified in 'ep' 526 ******************************************************************************/ 527 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 528 { 529 unsigned int security_state; 530 531 assert(ctx != NULL); 532 533 /* 534 * Perform initializations that are common 535 * to all security states 536 */ 537 setup_context_common(ctx, ep); 538 539 security_state = GET_SECURITY_STATE(ep->h.attr); 540 541 /* Perform security state specific initializations */ 542 switch (security_state) { 543 case SECURE: 544 setup_secure_context(ctx, ep); 545 break; 546 #if ENABLE_RME 547 case REALM: 548 setup_realm_context(ctx, ep); 549 break; 550 #endif 551 case NON_SECURE: 552 setup_ns_context(ctx, ep); 553 break; 554 default: 555 ERROR("Invalid security state\n"); 556 panic(); 557 break; 558 } 559 } 560 561 /******************************************************************************* 562 * Enable architecture extensions for EL3 execution. This function only updates 563 * registers in-place which are expected to either never change or be 564 * overwritten by el3_exit. 565 ******************************************************************************/ 566 #if IMAGE_BL31 567 void cm_manage_extensions_el3(void) 568 { 569 if (is_feat_spe_supported()) { 570 spe_init_el3(); 571 } 572 573 if (is_feat_amu_supported()) { 574 amu_init_el3(); 575 } 576 577 if (is_feat_sme_supported()) { 578 sme_init_el3(); 579 } 580 581 if (is_feat_mpam_supported()) { 582 mpam_init_el3(); 583 } 584 585 if (is_feat_trbe_supported()) { 586 trbe_init_el3(); 587 } 588 589 if (is_feat_brbe_supported()) { 590 brbe_init_el3(); 591 } 592 593 if (is_feat_trf_supported()) { 594 trf_init_el3(); 595 } 596 597 pmuv3_init_el3(); 598 } 599 #endif /* IMAGE_BL31 */ 600 601 /******************************************************************************* 602 * Enable architecture extensions on first entry to Non-secure world. 603 ******************************************************************************/ 604 static void manage_extensions_nonsecure(cpu_context_t *ctx) 605 { 606 #if IMAGE_BL31 607 if (is_feat_amu_supported()) { 608 amu_enable(ctx); 609 } 610 611 /* Enable SVE and FPU/SIMD */ 612 if (is_feat_sve_supported()) { 613 sve_enable(ctx); 614 } 615 616 if (is_feat_sme_supported()) { 617 sme_enable(ctx); 618 } 619 620 if (is_feat_sys_reg_trace_supported()) { 621 sys_reg_trace_enable(ctx); 622 } 623 624 pmuv3_enable(ctx); 625 #endif /* IMAGE_BL31 */ 626 } 627 628 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 629 static __unused void enable_pauth_el2(void) 630 { 631 u_register_t hcr_el2 = read_hcr_el2(); 632 /* 633 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 634 * accessing key registers or using pointer authentication instructions 635 * from lower ELs. 636 */ 637 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 638 639 write_hcr_el2(hcr_el2); 640 } 641 642 /******************************************************************************* 643 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 644 * world when EL2 is empty and unused. 645 ******************************************************************************/ 646 static void manage_extensions_nonsecure_el2_unused(void) 647 { 648 #if IMAGE_BL31 649 if (is_feat_spe_supported()) { 650 spe_init_el2_unused(); 651 } 652 653 if (is_feat_amu_supported()) { 654 amu_init_el2_unused(); 655 } 656 657 if (is_feat_mpam_supported()) { 658 mpam_init_el2_unused(); 659 } 660 661 if (is_feat_trbe_supported()) { 662 trbe_init_el2_unused(); 663 } 664 665 if (is_feat_sys_reg_trace_supported()) { 666 sys_reg_trace_init_el2_unused(); 667 } 668 669 if (is_feat_trf_supported()) { 670 trf_init_el2_unused(); 671 } 672 673 pmuv3_init_el2_unused(); 674 675 if (is_feat_sve_supported()) { 676 sve_init_el2_unused(); 677 } 678 679 if (is_feat_sme_supported()) { 680 sme_init_el2_unused(); 681 } 682 683 #if ENABLE_PAUTH 684 enable_pauth_el2(); 685 #endif /* ENABLE_PAUTH */ 686 #endif /* IMAGE_BL31 */ 687 } 688 689 /******************************************************************************* 690 * Enable architecture extensions on first entry to Secure world. 691 ******************************************************************************/ 692 static void manage_extensions_secure(cpu_context_t *ctx) 693 { 694 #if IMAGE_BL31 695 if (is_feat_sve_supported()) { 696 if (ENABLE_SVE_FOR_SWD) { 697 /* 698 * Enable SVE and FPU in secure context, secure manager must 699 * ensure that the SVE and FPU register contexts are properly 700 * managed. 701 */ 702 sve_enable(ctx); 703 } else { 704 /* 705 * Disable SVE and FPU in secure context so non-secure world 706 * can safely use them. 707 */ 708 sve_disable(ctx); 709 } 710 } 711 712 if (is_feat_sme_supported()) { 713 if (ENABLE_SME_FOR_SWD) { 714 /* 715 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 716 * must ensure SME, SVE, and FPU/SIMD context properly managed. 717 */ 718 sme_init_el3(); 719 sme_enable(ctx); 720 } else { 721 /* 722 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 723 * world can safely use the associated registers. 724 */ 725 sme_disable(ctx); 726 } 727 } 728 729 /* NS can access this but Secure shouldn't */ 730 if (is_feat_sys_reg_trace_supported()) { 731 sys_reg_trace_disable(ctx); 732 } 733 #endif /* IMAGE_BL31 */ 734 } 735 736 /******************************************************************************* 737 * The following function initializes the cpu_context for a CPU specified by 738 * its `cpu_idx` for first use, and sets the initial entrypoint state as 739 * specified by the entry_point_info structure. 740 ******************************************************************************/ 741 void cm_init_context_by_index(unsigned int cpu_idx, 742 const entry_point_info_t *ep) 743 { 744 cpu_context_t *ctx; 745 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 746 cm_setup_context(ctx, ep); 747 } 748 749 /******************************************************************************* 750 * The following function initializes the cpu_context for the current CPU 751 * for first use, and sets the initial entrypoint state as specified by the 752 * entry_point_info structure. 753 ******************************************************************************/ 754 void cm_init_my_context(const entry_point_info_t *ep) 755 { 756 cpu_context_t *ctx; 757 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 758 cm_setup_context(ctx, ep); 759 } 760 761 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 762 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 763 { 764 u_register_t hcr_el2 = HCR_RESET_VAL; 765 u_register_t mdcr_el2; 766 u_register_t scr_el3; 767 768 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 769 770 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 771 if ((scr_el3 & SCR_RW_BIT) != 0U) { 772 hcr_el2 |= HCR_RW_BIT; 773 } 774 775 write_hcr_el2(hcr_el2); 776 777 /* 778 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 779 * All fields have architecturally UNKNOWN reset values. 780 */ 781 write_cptr_el2(CPTR_EL2_RESET_VAL); 782 783 /* 784 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 785 * reset and are set to zero except for field(s) listed below. 786 * 787 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 788 * Non-secure EL0 and EL1 accesses to the physical timer registers. 789 * 790 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 791 * Non-secure EL0 and EL1 accesses to the physical counter registers. 792 */ 793 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 794 795 /* 796 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 797 * UNKNOWN value. 798 */ 799 write_cntvoff_el2(0); 800 801 /* 802 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 803 * respectively. 804 */ 805 write_vpidr_el2(read_midr_el1()); 806 write_vmpidr_el2(read_mpidr_el1()); 807 808 /* 809 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 810 * 811 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 812 * translation is disabled, cache maintenance operations depend on the 813 * VMID. 814 * 815 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 816 * disabled. 817 */ 818 write_vttbr_el2(VTTBR_RESET_VAL & 819 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 820 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 821 822 /* 823 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 824 * Some fields are architecturally UNKNOWN on reset. 825 * 826 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 827 * register accesses to the Debug ROM registers are not trapped to EL2. 828 * 829 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 830 * accesses to the powerdown debug registers are not trapped to EL2. 831 * 832 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 833 * debug registers do not trap to EL2. 834 * 835 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 836 * EL2. 837 */ 838 mdcr_el2 = MDCR_EL2_RESET_VAL & 839 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 840 MDCR_EL2_TDE_BIT); 841 842 write_mdcr_el2(mdcr_el2); 843 844 /* 845 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 846 * 847 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 848 * EL1 accesses to System registers do not trap to EL2. 849 */ 850 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 851 852 /* 853 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 854 * reset. 855 * 856 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 857 * and prevent timer interrupts. 858 */ 859 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 860 861 manage_extensions_nonsecure_el2_unused(); 862 } 863 864 /******************************************************************************* 865 * Prepare the CPU system registers for first entry into realm, secure, or 866 * normal world. 867 * 868 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 869 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 870 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 871 * For all entries, the EL1 registers are initialized from the cpu_context 872 ******************************************************************************/ 873 void cm_prepare_el3_exit(uint32_t security_state) 874 { 875 u_register_t sctlr_elx, scr_el3; 876 cpu_context_t *ctx = cm_get_context(security_state); 877 878 assert(ctx != NULL); 879 880 if (security_state == NON_SECURE) { 881 uint64_t el2_implemented = el_implemented(2); 882 883 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 884 CTX_SCR_EL3); 885 886 if (((scr_el3 & SCR_HCE_BIT) != 0U) 887 || (el2_implemented != EL_IMPL_NONE)) { 888 /* 889 * If context is not being used for EL2, initialize 890 * HCRX_EL2 with its init value here. 891 */ 892 if (is_feat_hcx_supported()) { 893 write_hcrx_el2(HCRX_EL2_INIT_VAL); 894 } 895 896 /* 897 * Initialize Fine-grained trap registers introduced 898 * by FEAT_FGT so all traps are initially disabled when 899 * switching to EL2 or a lower EL, preventing undesired 900 * behavior. 901 */ 902 if (is_feat_fgt_supported()) { 903 /* 904 * Initialize HFG*_EL2 registers with a default 905 * value so legacy systems unaware of FEAT_FGT 906 * do not get trapped due to their lack of 907 * initialization for this feature. 908 */ 909 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 910 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 911 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 912 } 913 } 914 915 916 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 917 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 918 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 919 CTX_SCTLR_EL1); 920 sctlr_elx &= SCTLR_EE_BIT; 921 sctlr_elx |= SCTLR_EL2_RES1; 922 #if ERRATA_A75_764081 923 /* 924 * If workaround of errata 764081 for Cortex-A75 is used 925 * then set SCTLR_EL2.IESB to enable Implicit Error 926 * Synchronization Barrier. 927 */ 928 sctlr_elx |= SCTLR_IESB_BIT; 929 #endif 930 write_sctlr_el2(sctlr_elx); 931 } else if (el2_implemented != EL_IMPL_NONE) { 932 init_nonsecure_el2_unused(ctx); 933 } 934 } 935 936 cm_el1_sysregs_context_restore(security_state); 937 cm_set_next_eret_context(security_state); 938 } 939 940 #if CTX_INCLUDE_EL2_REGS 941 942 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 943 { 944 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 945 if (is_feat_amu_supported()) { 946 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 947 } 948 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 949 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 950 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 951 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 952 } 953 954 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 955 { 956 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 957 if (is_feat_amu_supported()) { 958 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 959 } 960 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 961 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 962 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 963 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 964 } 965 966 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 967 { 968 u_register_t mpam_idr = read_mpamidr_el1(); 969 970 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 971 972 /* 973 * The context registers that we intend to save would be part of the 974 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 975 */ 976 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 977 return; 978 } 979 980 /* 981 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 982 * MPAMIDR_HAS_HCR_BIT == 1. 983 */ 984 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 985 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 986 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 987 988 /* 989 * The number of MPAMVPM registers is implementation defined, their 990 * number is stored in the MPAMIDR_EL1 register. 991 */ 992 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 993 case 7: 994 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 995 __fallthrough; 996 case 6: 997 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 998 __fallthrough; 999 case 5: 1000 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1001 __fallthrough; 1002 case 4: 1003 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1004 __fallthrough; 1005 case 3: 1006 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1007 __fallthrough; 1008 case 2: 1009 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1010 __fallthrough; 1011 case 1: 1012 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1013 break; 1014 } 1015 } 1016 1017 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1018 { 1019 u_register_t mpam_idr = read_mpamidr_el1(); 1020 1021 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1022 1023 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1024 return; 1025 } 1026 1027 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1028 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1029 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1030 1031 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1032 case 7: 1033 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1034 __fallthrough; 1035 case 6: 1036 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1037 __fallthrough; 1038 case 5: 1039 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1040 __fallthrough; 1041 case 4: 1042 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1043 __fallthrough; 1044 case 3: 1045 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1046 __fallthrough; 1047 case 2: 1048 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1049 __fallthrough; 1050 case 1: 1051 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1052 break; 1053 } 1054 } 1055 1056 /* ----------------------------------------------------- 1057 * The following registers are not added: 1058 * AMEVCNTVOFF0<n>_EL2 1059 * AMEVCNTVOFF1<n>_EL2 1060 * ICH_AP0R<n>_EL2 1061 * ICH_AP1R<n>_EL2 1062 * ICH_LR<n>_EL2 1063 * ----------------------------------------------------- 1064 */ 1065 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1066 { 1067 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1068 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1069 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1070 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1071 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1072 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1073 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1074 if (CTX_INCLUDE_AARCH32_REGS) { 1075 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1076 } 1077 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1078 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1079 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1080 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1081 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1082 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1083 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1084 1085 /* 1086 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1087 * TODO: remove with root context 1088 */ 1089 u_register_t scr_el3 = read_scr_el3(); 1090 1091 write_scr_el3(scr_el3 | SCR_NS_BIT); 1092 isb(); 1093 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1094 1095 write_scr_el3(scr_el3); 1096 isb(); 1097 1098 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1099 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1100 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1101 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1102 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1103 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1104 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1105 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1106 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1107 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1108 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1109 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1110 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1111 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1112 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1113 } 1114 1115 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1116 { 1117 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1118 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1119 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1120 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1121 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1122 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1123 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1124 if (CTX_INCLUDE_AARCH32_REGS) { 1125 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1126 } 1127 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1128 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1129 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1130 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1131 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1132 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1133 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1134 1135 /* 1136 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1137 * TODO: remove with root context 1138 */ 1139 u_register_t scr_el3 = read_scr_el3(); 1140 1141 write_scr_el3(scr_el3 | SCR_NS_BIT); 1142 isb(); 1143 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1144 1145 write_scr_el3(scr_el3); 1146 isb(); 1147 1148 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1149 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1150 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1151 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1152 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1153 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1154 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1155 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1156 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1157 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1158 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1159 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1160 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1161 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1162 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1163 } 1164 1165 /******************************************************************************* 1166 * Save EL2 sysreg context 1167 ******************************************************************************/ 1168 void cm_el2_sysregs_context_save(uint32_t security_state) 1169 { 1170 cpu_context_t *ctx; 1171 el2_sysregs_t *el2_sysregs_ctx; 1172 1173 ctx = cm_get_context(security_state); 1174 assert(ctx != NULL); 1175 1176 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1177 1178 el2_sysregs_context_save_common(el2_sysregs_ctx); 1179 #if CTX_INCLUDE_MTE_REGS 1180 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1181 #endif 1182 if (is_feat_mpam_supported()) { 1183 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1184 } 1185 1186 if (is_feat_fgt_supported()) { 1187 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1188 } 1189 1190 if (is_feat_ecv_v2_supported()) { 1191 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, read_cntpoff_el2()); 1192 } 1193 1194 if (is_feat_vhe_supported()) { 1195 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, read_contextidr_el2()); 1196 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); 1197 } 1198 1199 if (is_feat_ras_supported()) { 1200 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, read_vdisr_el2()); 1201 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, read_vsesr_el2()); 1202 } 1203 1204 if (is_feat_nv2_supported()) { 1205 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, read_vncr_el2()); 1206 } 1207 1208 if (is_feat_trf_supported()) { 1209 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1210 } 1211 1212 if (is_feat_csv2_2_supported()) { 1213 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, read_scxtnum_el2()); 1214 } 1215 1216 if (is_feat_hcx_supported()) { 1217 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1218 } 1219 if (is_feat_tcr2_supported()) { 1220 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1221 } 1222 if (is_feat_sxpie_supported()) { 1223 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1224 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1225 } 1226 if (is_feat_s2pie_supported()) { 1227 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1228 } 1229 if (is_feat_sxpoe_supported()) { 1230 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1231 } 1232 if (is_feat_gcs_supported()) { 1233 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1234 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1235 } 1236 } 1237 1238 /******************************************************************************* 1239 * Restore EL2 sysreg context 1240 ******************************************************************************/ 1241 void cm_el2_sysregs_context_restore(uint32_t security_state) 1242 { 1243 cpu_context_t *ctx; 1244 el2_sysregs_t *el2_sysregs_ctx; 1245 1246 ctx = cm_get_context(security_state); 1247 assert(ctx != NULL); 1248 1249 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1250 1251 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1252 #if CTX_INCLUDE_MTE_REGS 1253 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1254 #endif 1255 if (is_feat_mpam_supported()) { 1256 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1257 } 1258 1259 if (is_feat_fgt_supported()) { 1260 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1261 } 1262 1263 if (is_feat_ecv_v2_supported()) { 1264 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2)); 1265 } 1266 1267 if (is_feat_vhe_supported()) { 1268 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1269 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1270 } 1271 1272 if (is_feat_ras_supported()) { 1273 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1274 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1275 } 1276 1277 if (is_feat_nv2_supported()) { 1278 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1279 } 1280 if (is_feat_trf_supported()) { 1281 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1282 } 1283 1284 if (is_feat_csv2_2_supported()) { 1285 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2)); 1286 } 1287 1288 if (is_feat_hcx_supported()) { 1289 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1290 } 1291 if (is_feat_tcr2_supported()) { 1292 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1293 } 1294 if (is_feat_sxpie_supported()) { 1295 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1296 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1297 } 1298 if (is_feat_s2pie_supported()) { 1299 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1300 } 1301 if (is_feat_sxpoe_supported()) { 1302 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1303 } 1304 if (is_feat_gcs_supported()) { 1305 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1306 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1307 } 1308 } 1309 #endif /* CTX_INCLUDE_EL2_REGS */ 1310 1311 /******************************************************************************* 1312 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1313 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1314 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1315 * cm_prepare_el3_exit function. 1316 ******************************************************************************/ 1317 void cm_prepare_el3_exit_ns(void) 1318 { 1319 #if CTX_INCLUDE_EL2_REGS 1320 #if ENABLE_ASSERTIONS 1321 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1322 assert(ctx != NULL); 1323 1324 /* Assert that EL2 is used. */ 1325 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1326 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1327 (el_implemented(2U) != EL_IMPL_NONE)); 1328 #endif /* ENABLE_ASSERTIONS */ 1329 1330 /* Restore EL2 and EL1 sysreg contexts */ 1331 cm_el2_sysregs_context_restore(NON_SECURE); 1332 cm_el1_sysregs_context_restore(NON_SECURE); 1333 cm_set_next_eret_context(NON_SECURE); 1334 #else 1335 cm_prepare_el3_exit(NON_SECURE); 1336 #endif /* CTX_INCLUDE_EL2_REGS */ 1337 } 1338 1339 /******************************************************************************* 1340 * The next four functions are used by runtime services to save and restore 1341 * EL1 context on the 'cpu_context' structure for the specified security 1342 * state. 1343 ******************************************************************************/ 1344 void cm_el1_sysregs_context_save(uint32_t security_state) 1345 { 1346 cpu_context_t *ctx; 1347 1348 ctx = cm_get_context(security_state); 1349 assert(ctx != NULL); 1350 1351 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1352 1353 #if IMAGE_BL31 1354 if (security_state == SECURE) 1355 PUBLISH_EVENT(cm_exited_secure_world); 1356 else 1357 PUBLISH_EVENT(cm_exited_normal_world); 1358 #endif 1359 } 1360 1361 void cm_el1_sysregs_context_restore(uint32_t security_state) 1362 { 1363 cpu_context_t *ctx; 1364 1365 ctx = cm_get_context(security_state); 1366 assert(ctx != NULL); 1367 1368 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1369 1370 #if IMAGE_BL31 1371 if (security_state == SECURE) 1372 PUBLISH_EVENT(cm_entering_secure_world); 1373 else 1374 PUBLISH_EVENT(cm_entering_normal_world); 1375 #endif 1376 } 1377 1378 /******************************************************************************* 1379 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1380 * given security state with the given entrypoint 1381 ******************************************************************************/ 1382 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1383 { 1384 cpu_context_t *ctx; 1385 el3_state_t *state; 1386 1387 ctx = cm_get_context(security_state); 1388 assert(ctx != NULL); 1389 1390 /* Populate EL3 state so that ERET jumps to the correct entry */ 1391 state = get_el3state_ctx(ctx); 1392 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1393 } 1394 1395 /******************************************************************************* 1396 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1397 * pertaining to the given security state 1398 ******************************************************************************/ 1399 void cm_set_elr_spsr_el3(uint32_t security_state, 1400 uintptr_t entrypoint, uint32_t spsr) 1401 { 1402 cpu_context_t *ctx; 1403 el3_state_t *state; 1404 1405 ctx = cm_get_context(security_state); 1406 assert(ctx != NULL); 1407 1408 /* Populate EL3 state so that ERET jumps to the correct entry */ 1409 state = get_el3state_ctx(ctx); 1410 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1411 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1412 } 1413 1414 /******************************************************************************* 1415 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1416 * pertaining to the given security state using the value and bit position 1417 * specified in the parameters. It preserves all other bits. 1418 ******************************************************************************/ 1419 void cm_write_scr_el3_bit(uint32_t security_state, 1420 uint32_t bit_pos, 1421 uint32_t value) 1422 { 1423 cpu_context_t *ctx; 1424 el3_state_t *state; 1425 u_register_t scr_el3; 1426 1427 ctx = cm_get_context(security_state); 1428 assert(ctx != NULL); 1429 1430 /* Ensure that the bit position is a valid one */ 1431 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1432 1433 /* Ensure that the 'value' is only a bit wide */ 1434 assert(value <= 1U); 1435 1436 /* 1437 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1438 * and set it to its new value. 1439 */ 1440 state = get_el3state_ctx(ctx); 1441 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1442 scr_el3 &= ~(1UL << bit_pos); 1443 scr_el3 |= (u_register_t)value << bit_pos; 1444 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1445 } 1446 1447 /******************************************************************************* 1448 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1449 * given security state. 1450 ******************************************************************************/ 1451 u_register_t cm_get_scr_el3(uint32_t security_state) 1452 { 1453 cpu_context_t *ctx; 1454 el3_state_t *state; 1455 1456 ctx = cm_get_context(security_state); 1457 assert(ctx != NULL); 1458 1459 /* Populate EL3 state so that ERET jumps to the correct entry */ 1460 state = get_el3state_ctx(ctx); 1461 return read_ctx_reg(state, CTX_SCR_EL3); 1462 } 1463 1464 /******************************************************************************* 1465 * This function is used to program the context that's used for exception 1466 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1467 * the required security state 1468 ******************************************************************************/ 1469 void cm_set_next_eret_context(uint32_t security_state) 1470 { 1471 cpu_context_t *ctx; 1472 1473 ctx = cm_get_context(security_state); 1474 assert(ctx != NULL); 1475 1476 cm_set_next_context(ctx); 1477 } 1478