1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 /* ARM_ROTPK_KEY_LEN includes DER header + raw key material */ 28 #if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) 29 #if TF_MBEDTLS_KEY_SIZE == 384 30 #define ARM_ROTPK_KEY_LEN 120 31 #else 32 #define ARM_ROTPK_KEY_LEN 91 33 #endif 34 #else 35 /* ROTPK key length for 2kB RSA-key */ 36 #define ARM_ROTPK_KEY_LEN 294 37 #endif 38 39 /* Special value used to verify platform parameters from BL2 to BL31 */ 40 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 41 42 #define ARM_SYSTEM_COUNT U(1) 43 44 #define ARM_CACHE_WRITEBACK_SHIFT 6 45 46 /* 47 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 48 * power levels have a 1:1 mapping with the MPIDR affinity levels. 49 */ 50 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 51 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 52 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 53 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 54 55 /* 56 * Macros for local power states in ARM platforms encoded by State-ID field 57 * within the power-state parameter. 58 */ 59 /* Local power state for power domains in Run state. */ 60 #define ARM_LOCAL_STATE_RUN U(0) 61 /* Local power state for retention. Valid only for CPU power domains */ 62 #define ARM_LOCAL_STATE_RET U(1) 63 /* Local power state for OFF/power-down. Valid for CPU and cluster power 64 domains */ 65 #define ARM_LOCAL_STATE_OFF U(2) 66 67 /* Memory location options for TSP */ 68 #define ARM_TRUSTED_SRAM_ID 0 69 #define ARM_TRUSTED_DRAM_ID 1 70 #define ARM_DRAM_ID 2 71 72 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 73 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 74 #else 75 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 76 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 77 78 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 79 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 80 81 /* The remaining Trusted SRAM is used to load the BL images */ 82 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 83 ARM_SHARED_RAM_SIZE) 84 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 85 ARM_SHARED_RAM_SIZE) 86 87 /* 88 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 89 * follows: 90 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 91 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 92 * - REALM DRAM: Reserved for Realm world if RME is enabled 93 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 94 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 95 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 96 * 97 * RME enabled(64MB) RME not enabled(16MB) 98 * -------------------- ------------------- 99 * | | | | 100 * | AP TZC (~28MB) | | AP TZC (~14MB) | 101 * -------------------- ------------------- 102 * | Event Log | | Event Log | 103 * | (4KB) | | (4KB) | 104 * -------------------- ------------------- 105 * | REALM (RMM) | | | 106 * | (32MB - 4KB) | | EL3 TZC (2MB) | 107 * -------------------- ------------------- 108 * | | | | 109 * | TF-A <-> RMM | | SCP TZC | 110 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 111 * -------------------- 112 * | | 113 * | EL3 TZC (3MB) | 114 * -------------------- 115 * | L1 GPT + SCP TZC | 116 * | (~1MB) | 117 * 0xFFFF_FFFF -------------------- 118 */ 119 #if ENABLE_RME 120 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 121 /* 122 * Define a region within the TZC secured DRAM for use by EL3 runtime 123 * firmware. This region is meant to be NOLOAD and will not be zero 124 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 125 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 126 */ 127 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 128 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 129 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 130 #define ARM_REALM_SIZE (UL(0x02000000) - \ 131 ARM_EL3_RMM_SHARED_SIZE) 132 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 133 #else 134 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 135 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 136 #define ARM_L1_GPT_SIZE UL(0) 137 #define ARM_REALM_SIZE UL(0) 138 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 139 #endif /* ENABLE_RME */ 140 141 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 142 ARM_DRAM1_SIZE - \ 143 (ARM_SCP_TZC_DRAM1_SIZE + \ 144 ARM_L1_GPT_SIZE)) 145 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 146 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 147 ARM_SCP_TZC_DRAM1_SIZE - 1U) 148 149 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 150 MEASURED_BOOT 151 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 152 153 #if ENABLE_RME 154 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 155 ARM_EVENT_LOG_DRAM1_SIZE) 156 #else 157 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 158 ARM_EVENT_LOG_DRAM1_SIZE) 159 #endif /* ENABLE_RME */ 160 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 161 ARM_EVENT_LOG_DRAM1_SIZE - \ 162 1U) 163 #else 164 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 165 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 166 167 #if ENABLE_RME 168 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 169 ARM_DRAM1_SIZE - \ 170 ARM_L1_GPT_SIZE) 171 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 172 ARM_L1_GPT_SIZE - 1U) 173 174 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 175 ARM_REALM_SIZE) 176 177 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 178 179 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 180 ARM_DRAM1_SIZE - \ 181 (ARM_SCP_TZC_DRAM1_SIZE + \ 182 ARM_L1_GPT_SIZE + \ 183 ARM_EL3_RMM_SHARED_SIZE + \ 184 ARM_EL3_TZC_DRAM1_SIZE)) 185 186 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 187 ARM_EL3_RMM_SHARED_SIZE - 1U) 188 #endif /* ENABLE_RME */ 189 190 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 191 ARM_EL3_TZC_DRAM1_SIZE) 192 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 193 ARM_EL3_TZC_DRAM1_SIZE - 1U) 194 195 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 196 ARM_DRAM1_SIZE - \ 197 ARM_TZC_DRAM1_SIZE) 198 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 199 (ARM_SCP_TZC_DRAM1_SIZE + \ 200 ARM_EL3_TZC_DRAM1_SIZE + \ 201 ARM_EL3_RMM_SHARED_SIZE + \ 202 ARM_REALM_SIZE + \ 203 ARM_L1_GPT_SIZE + \ 204 ARM_EVENT_LOG_DRAM1_SIZE)) 205 206 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 207 ARM_AP_TZC_DRAM1_SIZE - 1U) 208 209 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 210 #if ARM_CRYPTOCELL_INTEG 211 /* 212 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 213 * This is required by CryptoCell to authenticate BL33 which is loaded 214 * into the Non Secure DDR. 215 */ 216 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 217 #else 218 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 219 #endif 220 221 #ifdef SPD_opteed 222 /* 223 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 224 * load/authenticate the trusted os extra image. The first 512KB of 225 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 226 * for OPTEE is paged image which only include the paging part using 227 * virtual memory but without "init" data. OPTEE will copy the "init" data 228 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 229 * extra image behind the "init" data. 230 */ 231 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 232 ARM_AP_TZC_DRAM1_SIZE - \ 233 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 234 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 235 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 236 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 237 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 238 MT_MEMORY | MT_RW | MT_SECURE) 239 240 /* 241 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 242 * support is enabled). 243 */ 244 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 245 BL32_BASE, \ 246 BL32_LIMIT - BL32_BASE, \ 247 MT_MEMORY | MT_RW | MT_SECURE) 248 #endif /* SPD_opteed */ 249 250 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 251 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 252 ARM_TZC_DRAM1_SIZE) 253 254 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 255 ARM_NS_DRAM1_SIZE - 1U) 256 #ifdef PLAT_ARM_DRAM1_BASE 257 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 258 #else 259 #define ARM_DRAM1_BASE ULL(0x80000000) 260 #endif /* PLAT_ARM_DRAM1_BASE */ 261 262 #define ARM_DRAM1_SIZE ULL(0x80000000) 263 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 264 ARM_DRAM1_SIZE - 1U) 265 266 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 267 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 268 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 269 ARM_DRAM2_SIZE - 1U) 270 /* Number of DRAM banks */ 271 #define ARM_DRAM_NUM_BANKS 2UL 272 273 #define ARM_IRQ_SEC_PHY_TIMER 29 274 275 #define ARM_IRQ_SEC_SGI_0 8 276 #define ARM_IRQ_SEC_SGI_1 9 277 #define ARM_IRQ_SEC_SGI_2 10 278 #define ARM_IRQ_SEC_SGI_3 11 279 #define ARM_IRQ_SEC_SGI_4 12 280 #define ARM_IRQ_SEC_SGI_5 13 281 #define ARM_IRQ_SEC_SGI_6 14 282 #define ARM_IRQ_SEC_SGI_7 15 283 284 /* 285 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 286 * terminology. On a GICv2 system or mode, the lists will be merged and treated 287 * as Group 0 interrupts. 288 */ 289 #define ARM_G1S_IRQ_PROPS(grp) \ 290 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 291 GIC_INTR_CFG_LEVEL), \ 292 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 293 GIC_INTR_CFG_EDGE), \ 294 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 295 GIC_INTR_CFG_EDGE), \ 296 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 297 GIC_INTR_CFG_EDGE), \ 298 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 299 GIC_INTR_CFG_EDGE), \ 300 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 301 GIC_INTR_CFG_EDGE), \ 302 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 303 GIC_INTR_CFG_EDGE) 304 305 #define ARM_G0_IRQ_PROPS(grp) \ 306 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 307 GIC_INTR_CFG_EDGE), \ 308 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 309 GIC_INTR_CFG_EDGE) 310 311 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 312 ARM_SHARED_RAM_BASE, \ 313 ARM_SHARED_RAM_SIZE, \ 314 MT_DEVICE | MT_RW | EL3_PAS) 315 316 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 317 ARM_NS_DRAM1_BASE, \ 318 ARM_NS_DRAM1_SIZE, \ 319 MT_MEMORY | MT_RW | MT_NS) 320 321 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 322 ARM_DRAM2_BASE, \ 323 ARM_DRAM2_SIZE, \ 324 MT_MEMORY | MT_RW | MT_NS) 325 326 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 327 TSP_SEC_MEM_BASE, \ 328 TSP_SEC_MEM_SIZE, \ 329 MT_MEMORY | MT_RW | MT_SECURE) 330 331 #if ARM_BL31_IN_DRAM 332 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 333 BL31_BASE, \ 334 PLAT_ARM_MAX_BL31_SIZE, \ 335 MT_MEMORY | MT_RW | MT_SECURE) 336 #endif 337 338 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 339 ARM_EL3_TZC_DRAM1_BASE, \ 340 ARM_EL3_TZC_DRAM1_SIZE, \ 341 MT_MEMORY | MT_RW | EL3_PAS) 342 343 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 344 PLAT_ARM_TRUSTED_DRAM_BASE, \ 345 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 346 MT_MEMORY | MT_RW | MT_SECURE) 347 348 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 349 MEASURED_BOOT 350 #define ARM_MAP_EVENT_LOG_DRAM1 \ 351 MAP_REGION_FLAT( \ 352 ARM_EVENT_LOG_DRAM1_BASE, \ 353 ARM_EVENT_LOG_DRAM1_SIZE, \ 354 MT_MEMORY | MT_RW | MT_SECURE) 355 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 356 357 #if ENABLE_RME 358 /* 359 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 360 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 361 */ 362 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 363 PLAT_ARM_RMM_BASE, \ 364 (PLAT_ARM_RMM_SIZE + \ 365 ARM_EL3_RMM_SHARED_SIZE), \ 366 MT_MEMORY | MT_RW | MT_REALM) 367 368 369 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 370 ARM_L1_GPT_ADDR_BASE, \ 371 ARM_L1_GPT_SIZE, \ 372 MT_MEMORY | MT_RW | EL3_PAS) 373 374 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 375 MAP_REGION_FLAT( \ 376 ARM_EL3_RMM_SHARED_BASE, \ 377 ARM_EL3_RMM_SHARED_SIZE, \ 378 MT_MEMORY | MT_RW | MT_REALM) 379 380 #endif /* ENABLE_RME */ 381 382 /* 383 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 384 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 385 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 386 * to be able to access the heap. 387 */ 388 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 389 BL1_RW_BASE, \ 390 BL1_RW_LIMIT - BL1_RW_BASE, \ 391 MT_MEMORY | MT_RW | EL3_PAS) 392 393 /* 394 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 395 * otherwise one region is defined containing both. 396 */ 397 #if SEPARATE_CODE_AND_RODATA 398 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 399 BL_CODE_BASE, \ 400 BL_CODE_END - BL_CODE_BASE, \ 401 MT_CODE | EL3_PAS), \ 402 MAP_REGION_FLAT( \ 403 BL_RO_DATA_BASE, \ 404 BL_RO_DATA_END \ 405 - BL_RO_DATA_BASE, \ 406 MT_RO_DATA | EL3_PAS) 407 #else 408 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 409 BL_CODE_BASE, \ 410 BL_CODE_END - BL_CODE_BASE, \ 411 MT_CODE | EL3_PAS) 412 #endif 413 #if USE_COHERENT_MEM 414 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 415 BL_COHERENT_RAM_BASE, \ 416 BL_COHERENT_RAM_END \ 417 - BL_COHERENT_RAM_BASE, \ 418 MT_DEVICE | MT_RW | EL3_PAS) 419 #endif 420 #if USE_ROMLIB 421 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 422 ROMLIB_RO_BASE, \ 423 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 424 MT_CODE | EL3_PAS) 425 426 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 427 ROMLIB_RW_BASE, \ 428 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 429 MT_MEMORY | MT_RW | EL3_PAS) 430 #endif 431 432 /* 433 * Map mem_protect flash region with read and write permissions 434 */ 435 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 436 V2M_FLASH_BLOCK_SIZE, \ 437 MT_DEVICE | MT_RW | MT_SECURE) 438 /* 439 * Map the region for device tree configuration with read and write permissions 440 */ 441 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 442 (ARM_FW_CONFIGS_LIMIT \ 443 - ARM_BL_RAM_BASE), \ 444 MT_MEMORY | MT_RW | EL3_PAS) 445 /* 446 * Map L0_GPT with read and write permissions 447 */ 448 #if ENABLE_RME 449 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 450 ARM_L0_GPT_SIZE, \ 451 MT_MEMORY | MT_RW | MT_ROOT) 452 #endif 453 454 /* 455 * The max number of regions like RO(code), coherent and data required by 456 * different BL stages which need to be mapped in the MMU. 457 */ 458 #define ARM_BL_REGIONS 7 459 460 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 461 ARM_BL_REGIONS) 462 463 /* Memory mapped Generic timer interfaces */ 464 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 465 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 466 #else 467 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 468 #endif 469 470 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 471 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 472 #else 473 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 474 #endif 475 476 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 477 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 478 #else 479 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 480 #endif 481 482 #ifdef PLAT_ARM_SYS_CNT_BASE_S 483 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 484 #else 485 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 486 #endif 487 488 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 489 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 490 #else 491 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 492 #endif 493 494 #define ARM_CONSOLE_BAUDRATE 115200 495 496 /* Trusted Watchdog constants */ 497 #ifdef PLAT_ARM_SP805_TWDG_BASE 498 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 499 #else 500 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 501 #endif 502 #define ARM_SP805_TWDG_CLK_HZ 32768 503 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 504 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 505 #define ARM_TWDG_TIMEOUT_SEC 128 506 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 507 ARM_TWDG_TIMEOUT_SEC) 508 509 /****************************************************************************** 510 * Required platform porting definitions common to all ARM standard platforms 511 *****************************************************************************/ 512 513 /* 514 * This macro defines the deepest retention state possible. A higher state 515 * id will represent an invalid or a power down state. 516 */ 517 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 518 519 /* 520 * This macro defines the deepest power down states possible. Any state ID 521 * higher than this is invalid. 522 */ 523 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 524 525 /* 526 * Some data must be aligned on the biggest cache line size in the platform. 527 * This is known only to the platform as it might have a combination of 528 * integrated and external caches. 529 */ 530 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 531 532 /* 533 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 534 * and limit. Leave enough space of BL2 meminfo. 535 */ 536 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 537 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 538 + (PAGE_SIZE / 2U)) 539 540 /* 541 * Boot parameters passed from BL2 to BL31/BL32 are stored here 542 */ 543 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 544 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 545 + (PAGE_SIZE / 2U)) 546 547 /* 548 * Define limit of firmware configuration memory: 549 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 550 */ 551 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 552 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 553 554 #if ENABLE_RME 555 /* 556 * Store the L0 GPT on Trusted SRAM next to firmware 557 * configuration memory, 4KB aligned. 558 */ 559 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 560 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 561 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 562 #else 563 #define ARM_L0_GPT_SIZE U(0) 564 #endif 565 566 /******************************************************************************* 567 * BL1 specific defines. 568 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 569 * addresses. 570 ******************************************************************************/ 571 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 572 #ifdef PLAT_BL1_RO_LIMIT 573 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 574 #else 575 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 576 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 577 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 578 #endif 579 580 /* 581 * Put BL1 RW at the top of the Trusted SRAM. 582 */ 583 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 584 ARM_BL_RAM_SIZE - \ 585 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 586 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 587 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 588 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 589 590 #define ROMLIB_RO_BASE BL1_RO_LIMIT 591 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 592 593 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 594 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 595 596 /******************************************************************************* 597 * BL2 specific defines. 598 ******************************************************************************/ 599 #if RESET_TO_BL2 600 #if ENABLE_PIE 601 /* 602 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 603 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 604 */ 605 #define BL2_OFFSET (0x5000) 606 #else 607 /* Put BL2 towards the middle of the Trusted SRAM */ 608 #define BL2_OFFSET (0x2000) 609 #endif /* ENABLE_PIE */ 610 611 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 612 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 613 BL2_OFFSET) 614 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 615 616 #else 617 /* 618 * Put BL2 just below BL1. 619 */ 620 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 621 #define BL2_LIMIT BL1_RW_BASE 622 #endif 623 624 /******************************************************************************* 625 * BL31 specific defines. 626 ******************************************************************************/ 627 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 628 /* 629 * Put BL31 at the bottom of TZC secured DRAM 630 */ 631 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 632 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 633 PLAT_ARM_MAX_BL31_SIZE) 634 /* 635 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 636 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 637 */ 638 #if SEPARATE_NOBITS_REGION 639 #define BL31_NOBITS_BASE BL2_BASE 640 #define BL31_NOBITS_LIMIT BL2_LIMIT 641 #endif /* SEPARATE_NOBITS_REGION */ 642 #elif (RESET_TO_BL31) 643 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 644 # if !ENABLE_PIE 645 # error "BL31 must be a PIE if RESET_TO_BL31=1." 646 #endif 647 /* 648 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 649 * used for building BL31 and not used for loading BL31. 650 */ 651 # define BL31_BASE 0x0 652 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 653 #else 654 /* Put BL31 below BL2 in the Trusted SRAM.*/ 655 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 656 - PLAT_ARM_MAX_BL31_SIZE) 657 #define BL31_PROGBITS_LIMIT BL2_BASE 658 /* 659 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 660 * This is because in the RESET_TO_BL2 configuration, 661 * BL2 is always resident. 662 */ 663 #if RESET_TO_BL2 664 #define BL31_LIMIT BL2_BASE 665 #else 666 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 667 #endif 668 #endif 669 670 /****************************************************************************** 671 * RMM specific defines 672 *****************************************************************************/ 673 #if ENABLE_RME 674 #define RMM_BASE (ARM_REALM_BASE) 675 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 676 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 677 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 678 #endif 679 680 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 681 /******************************************************************************* 682 * BL32 specific defines for EL3 runtime in AArch32 mode 683 ******************************************************************************/ 684 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 685 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 686 # if !ENABLE_PIE 687 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 688 #endif 689 /* 690 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 691 * used for building BL32 and not used for loading BL32. 692 */ 693 # define BL32_BASE 0x0 694 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 695 # else 696 /* Put BL32 below BL2 in the Trusted SRAM.*/ 697 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 698 - PLAT_ARM_MAX_BL32_SIZE) 699 # define BL32_PROGBITS_LIMIT BL2_BASE 700 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 701 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 702 703 #else 704 /******************************************************************************* 705 * BL32 specific defines for EL3 runtime in AArch64 mode 706 ******************************************************************************/ 707 /* 708 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 709 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 710 * controller. 711 */ 712 # if SPM_MM || SPMC_AT_EL3 713 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 714 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 715 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 716 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 717 ARM_AP_TZC_DRAM1_SIZE) 718 # elif defined(SPD_spmd) 719 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 720 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 721 # define BL32_BASE PLAT_ARM_SPMC_BASE 722 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 723 PLAT_ARM_SPMC_SIZE) 724 # elif ARM_BL31_IN_DRAM 725 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 726 PLAT_ARM_MAX_BL31_SIZE) 727 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 728 PLAT_ARM_MAX_BL31_SIZE) 729 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 730 PLAT_ARM_MAX_BL31_SIZE) 731 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 732 ARM_AP_TZC_DRAM1_SIZE) 733 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 734 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 735 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 736 # define TSP_PROGBITS_LIMIT BL31_BASE 737 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 738 # define BL32_LIMIT BL31_BASE 739 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 740 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 741 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 742 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 743 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 744 + SZ_4M) 745 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 746 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 747 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 748 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 749 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 750 ARM_AP_TZC_DRAM1_SIZE) 751 # else 752 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 753 # endif 754 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 755 756 /* 757 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 758 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 759 * used as BL32. 760 */ 761 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 762 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 763 # undef BL32_BASE 764 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 765 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 766 767 /******************************************************************************* 768 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 769 ******************************************************************************/ 770 #define BL2U_BASE BL2_BASE 771 #define BL2U_LIMIT BL2_LIMIT 772 773 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 774 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 775 776 /* 777 * ID of the secure physical generic timer interrupt used by the TSP. 778 */ 779 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 780 781 782 /* 783 * One cache line needed for bakery locks on ARM platforms 784 */ 785 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 786 787 /* Priority levels for ARM platforms */ 788 #if RAS_FFH_SUPPORT 789 #define PLAT_RAS_PRI 0x10 790 #endif 791 #define PLAT_SDEI_CRITICAL_PRI 0x60 792 #define PLAT_SDEI_NORMAL_PRI 0x70 793 794 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 795 #define PLAT_CORE_FAULT_IRQ 17 796 797 /* ARM platforms use 3 upper bits of secure interrupt priority */ 798 #define PLAT_PRI_BITS 3 799 800 /* SGI used for SDEI signalling */ 801 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 802 803 #if SDEI_IN_FCONF 804 /* ARM SDEI dynamic private event max count */ 805 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 806 807 /* ARM SDEI dynamic shared event max count */ 808 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 809 #else 810 /* ARM SDEI dynamic private event numbers */ 811 #define ARM_SDEI_DP_EVENT_0 1000 812 #define ARM_SDEI_DP_EVENT_1 1001 813 #define ARM_SDEI_DP_EVENT_2 1002 814 815 /* ARM SDEI dynamic shared event numbers */ 816 #define ARM_SDEI_DS_EVENT_0 2000 817 #define ARM_SDEI_DS_EVENT_1 2001 818 #define ARM_SDEI_DS_EVENT_2 2002 819 820 #define ARM_SDEI_PRIVATE_EVENTS \ 821 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 822 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 823 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 824 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 825 826 #define ARM_SDEI_SHARED_EVENTS \ 827 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 828 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 829 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 830 #endif /* SDEI_IN_FCONF */ 831 832 #endif /* ARM_DEF_H */ 833