fix(docs): fix the example command for doc build

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I8ee666ee4cd135d09380ce31751ddba9962ff831

docs: el3 token signing

Add documentation for the feature where EL3 can be used to sign realm
attestation token requests using RMM_EL3_TOKEN_SIGN command.
This patch also adds documentation for the

docs: el3 token signing

Add documentation for the feature where EL3 can be used to sign realm
attestation token requests using RMM_EL3_TOKEN_SIGN command.
This patch also adds documentation for the RMM_EL3_FEATURES features
command that can be used to discover support for features such as
RMM_EL3_TOKEN_SIGN.

Change-Id: Iab5a157761ed17931210c3702f813198fc9c4b3a
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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feat(docs): add DPE to RSE desing doc

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Iec38be8a3eb93a54d9b5bc7db7a7ff8c126920ac

feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I23

feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I234a2400d00fea606c5312ebddf94e2624463ff8

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feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the poss

feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the possible attacks.
- Rephrase the section that describes the Measured Boot backends.

Change-Id: I6577a56184992bf16f4aa1b773d1636781cbb049
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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fix(docs): fix the indent and the build command for MT8188

This patch includes
- Fix the indent.
- LD argument is no longer needed. Remove LD parameter from the build
command.

Change-Id: I615704c

fix(docs): fix the indent and the build command for MT8188

This patch includes
- Fix the indent.
- LD argument is no longer needed. Remove LD parameter from the build
command.

Change-Id: I615704cf6f4b6fd9e37c047b18c40f00652e269d
Signed-off-by: Yidi Lin <yidilin@chromium.org>

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Merge "feat(d128): add support for FEAT_D128" into integration

Merge "fix(mte): remove deprecated CTX_INCLUDE_MTE_REGS/FEAT_MTE" into integration

feat(d128): add support for FEAT_D128

This patch disables trapping to EL3 when the FEAT_D128
specific registers are accessed by setting the SCR_EL3.D128En bit.

If FEAT_D128 is implemented, then FEA

feat(d128): add support for FEAT_D128

This patch disables trapping to EL3 when the FEAT_D128
specific registers are accessed by setting the SCR_EL3.D128En bit.

If FEAT_D128 is implemented, then FEAT_SYSREG128 is implemented.
With FEAT_SYSREG128 certain system registers are treated as 128-bit,
so we should be context saving and restoring 128-bits instead of 64-bit
when FEAT_D128 is enabled.

FEAT_SYSREG128 adds support for MRRS and MSRR instruction which
helps us to read write to 128-bit system register.
Refer to Arm Architecture Manual for further details.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I1a53db5eac29e56c8fbdcd4961ede3abfcb2411a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(mte): remove deprecated CTX_INCLUDE_MTE_REGS/FEAT_MTE

Remove all instances of macros CTX_INCLUDE_MTE_REGS and FEAT_MTE
since these have been deprecated in v2.11

Change-Id: I7838a865755326f03668

fix(mte): remove deprecated CTX_INCLUDE_MTE_REGS/FEAT_MTE

Remove all instances of macros CTX_INCLUDE_MTE_REGS and FEAT_MTE
since these have been deprecated in v2.11

Change-Id: I7838a865755326f03668e43768140929a2d9e418
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "docs: add Govind as new TF-A maintainer" into integration

docs: add Govind as new TF-A maintainer

Also update Raghu's email address.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Icea15fa5eaf5413b0be7c42e8ef376cfeb9d5f27

Merge "feat(sctlr2): add support for FEAT_SCTLR2" into integration

Merge "feat(the): add support for FEAT_THE" into integration

docs: update TF-A May'25 release dates

Tentatively updating the plan for TF-A v2.13 release in May'25.

Change-Id: I98abe5f72901b71179a1efe3762046756d5ab6ac
Signed-off-by: Govindraj Raja <govindraj.

docs: update TF-A May'25 release dates

Tentatively updating the plan for TF-A v2.13 release in May'25.

Change-Id: I98abe5f72901b71179a1efe3762046756d5ab6ac
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(sctlr2): add support for FEAT_SCTLR2

Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the

feat(sctlr2): add support for FEAT_SCTLR2

Arm v8.9 introduces FEAT_SCTLR2, adding SCTLR2_ELx registers.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I0c4cba86917b6b065a7e8dd6af7daf64ee18dcda
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(the): add support for FEAT_THE

Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switchin

feat(the): add support for FEAT_THE

Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I8775787f523639b39faf61d046ef482f73b2a562
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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docs(maintainers): update qti maintainer

Add Saurabh Gorecha in qti maintainer

Change-Id: I24c8453288444ec9f60dca7c4019fd1635090b33
Signed-off-by: Bharath N <quic_bharn@quicinc.com>

docs: deprecate Arm TC2 FVP platform

Arm has made the strategic decision to deprecate the TC2 platform. As
a result, software development and the creation of fast models for TC2
have been officially

docs: deprecate Arm TC2 FVP platform

Arm has made the strategic decision to deprecate the TC2 platform. As
a result, software development and the creation of fast models for TC2
have been officially discontinued. The TC2 platform, now considered
obsolete, has been succeeded by the TC3 and TC4 platforms. Notably,
both TC3 and TC4 are already integrated into TF-A, with TC3 included
in the CI repository. Work to add CI support for TC4 is currently in
progress.

Change-Id: I4df3c3e947faa1849a0f4742593c604cb2ee43b9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(cpus): workaround for Cortex-X4 erratum 3076789" into integration

Merge "docs(build): update GCC to 13.3.Rel1 version" into integration

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL31 for RD-1 AE platform
feat(rd1ae): add device tree files
feat(rd1ae): introduce Arm RD-1 AE platform
build(bl2): enable check for bl2 base overflow assert
feat(arm): add support for loading CONFIG from BL2

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docs(build): update GCC to 13.3.Rel1 version

Updating toolchain to the latest production release version
13.3.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-down

docs(build): update GCC to 13.3.Rel1 version

Updating toolchain to the latest production release version
13.3.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads

We build TF-A in CI using x86_64 Linux hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: If5915fdc14a6c65ce58ac7fccfddd6fe85c0d7c9

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fix(cpus): workaround for Cortex-X4 erratum 3076789

Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set chicken bits

fix(cpus): workaround for Cortex-X4 erratum 3076789

Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set chicken bits CPUACTLR3_EL1[14:13]=0b11
and CPUACTLR_EL1[52] = 1.
Expected performance degradation is < 0.5%, but isolated
benchmark components might see higher impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ib100bfab91efdb6330fdcdac127bcc5732d59196
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "nxp-s32g274a/err051700" into integration

* changes:
feat(s32g274a): enable workaround for ERR051700
fix(s32g274a): workaround for ERR051700 erratum