1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53 54- `Cortex-A53 MPCore Software Developers Errata Notice`_ 55- `Cortex-A57 MPCore Software Developers Errata Notice`_ 56- `Cortex-A72 MPCore Software Developers Errata Notice`_ 57 58The errata workarounds are implemented for a particular revision or a set of 59processor revisions. This is checked by the reset handler at runtime. Each 60errata workaround is identified by its ``ID`` as specified in the processor's 61errata notice document. The format of the define used to enable/disable the 62errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 63is for example ``A57`` for the ``Cortex_A57`` CPU. 64 65Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 66write errata workaround functions. 67 68All workarounds are disabled by default. The platform is responsible for 69enabling these workarounds according to its requirement by defining the 70errata workaround build flags in the platform specific makefile. In case 71these workarounds are enabled for the wrong CPU revision then the errata 72workaround is not applied. In the DEBUG build, this is indicated by 73printing a warning to the crash console. 74 75In the current implementation, a platform which has more than 1 variant 76with different revisions of a processor has no runtime mechanism available 77for it to specify which errata workarounds should be enabled or not. 78 79The value of the build flags is 0 by default, that is, disabled. A value of 1 80will enable it. 81 82For Cortex-A9, the following errata build flags are defined : 83 84- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 85 CPU. This needs to be enabled for all revisions of the CPU. 86 87For Cortex-A15, the following errata build flags are defined : 88 89- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 93 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 94 95For Cortex-A17, the following errata build flags are defined : 96 97- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 101 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 102 103For Cortex-A35, the following errata build flags are defined : 104 105- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 106 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 107 108For Cortex-A53, the following errata build flags are defined : 109 110- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 112 113- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 114 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 115 116- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 117 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 118 119- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 120 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 121 122- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 123 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 124 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 125 sections. 126 127- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 128 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 129 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 130 ``A53_DISABLE_NON_TEMPORAL_HINT``. 131 132- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 133 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 134 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 135 which are 4kB aligned. 136 137- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 138 CPUs. Though the erratum is present in every revision of the CPU, 139 this workaround is only applied to CPUs from r0p3 onwards, which feature 140 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 141 Earlier revisions of the CPU have other errata which require the same 142 workaround in software, so they should be covered anyway. 143 144- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 145 revisions of Cortex-A53 CPU. 146 147For Cortex-A55, the following errata build flags are defined : 148 149- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision r0p0 of the CPU. 157 158- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 163 164- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 165 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 166 167- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 168 revisions of Cortex-A55 CPU. 169 170For Cortex-A57, the following errata build flags are defined : 171 172- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision r0p0 of the CPU. 183 184- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 186 187- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 195 196- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 201 202- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 203 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 204 205- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 206 revisions of Cortex-A57 CPU. 207 208For Cortex-A72, the following errata build flags are defined : 209 210- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 211 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 212 213- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 214 revisions of Cortex-A72 CPU. 215 216For Cortex-A73, the following errata build flags are defined : 217 218- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 219 CPU. This needs to be enabled only for revision r0p0 of the CPU. 220 221- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 222 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 223 224For Cortex-A75, the following errata build flags are defined : 225 226- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 227 CPU. This needs to be enabled only for revision r0p0 of the CPU. 228 229- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 230 CPU. This needs to be enabled only for revision r0p0 of the CPU. 231 232For Cortex-A76, the following errata build flags are defined : 233 234- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 235 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 236 237- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 238 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 239 240- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 241 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 242 243- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 244 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 245 246- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 247 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 248 249- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 250 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 251 252- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 253 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 254 255- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 256 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 257 258- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 259 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 260 limitation of errata framework this errata is applied to all revisions 261 of Cortex-A76 CPU. 262 263- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 264 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 265 266- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 267 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 268 269- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 270 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 271 still open. 272 273For Cortex-A77, the following errata build flags are defined : 274 275- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 276 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 277 278- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 279 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 280 281- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 282 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 283 284- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 285 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 286 287- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 288 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 289 290 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 291 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 292 293 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 294 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 295 296For Cortex-A78, the following errata build flags are defined : 297 298- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 299 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 300 301- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 302 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 303 304- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 305 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 306 issue but there is no workaround for that revision. 307 308- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 309 CPU. This needs to be enabled for revisions r0p0 and r1p0. 310 311- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 312 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 313 314- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 315 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 316 is still open. 317 318- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 319 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 320 is present in r0p0 but there is no workaround. It is still open. 321 322- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 323 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 324 it is still open. 325 326- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 327 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 328 it is still open. 329 330- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 331 CPU, this erratum affects system configurations that do not use an ARM 332 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 333 and r1p2 and it is still open. 334 335- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 336 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 337 it is still open. 338 339- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 340 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 341 it is still open. 342 343- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 344 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 345 it is still open. 346 347For Cortex-A78AE, the following errata build flags are defined : 348 349- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 350 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 351 This erratum is still open. 352 353- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 354 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 355 erratum is still open. 356 357- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 358 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 359 This erratum is still open. 360 361- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 362 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 363 erratum is still open. 364 365- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 366 Cortex-A78AE CPU. This erratum affects system configurations that do not use 367 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 368 r0p2. This erratum is still open. 369 370For Cortex-A78C, the following errata build flags are defined : 371 372- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 373 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 374 fixed in r0p1. 375 376- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 377 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 378 fixed in r0p1. 379 380- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to 381 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 382 it is still open. 383 384- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 385 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 386 it is still open. 387 388- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 389 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 390 erratum is still open. 391 392- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 393 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 394 erratum is still open. 395 396- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 397 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 398 erratum is still open. 399 400- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 401 Cortex-A78C CPU, this erratum affects system configurations that do not use 402 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 403 and is still open. 404 405- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 406 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 407 This erratum is still open. 408 409- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 410 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 411 This erratum is still open. 412 413- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 414 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 415 This erratum is still open. 416 417For Cortex-X1 CPU, the following errata build flags are defined: 418 419- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 420 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 421 422- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 423 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 424 425- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 426 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 427 428For Neoverse N1, the following errata build flags are defined : 429 430- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 431 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 432 433- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 434 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 435 436- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 437 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 438 439- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 440 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 441 442- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 443 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 444 445- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 446 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 447 448- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 449 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 450 451- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 452 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 453 454- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 455 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 456 457- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 458 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 459 460- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 461 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 462 463- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 464 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 465 466- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 467 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 468 revisions r0p0, r1p0, and r2p0 there is no workaround. 469 470- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 471 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 472 still open. 473 474For Neoverse V1, the following errata build flags are defined : 475 476- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 477 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 478 r1p0. 479 480- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 481 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 482 in r1p1. 483 484- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 485 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 486 in r1p1. 487 488- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 489 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 490 in r1p1. 491 492- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 493 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 494 495- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 496 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 497 CPU. 498 499- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 500 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 501 issue is present in r0p0 as well but there is no workaround for that 502 revision. It is still open. 503 504- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 505 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 506 CPU. It is still open. 507 508- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 509 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 510 It is still open. 511 512- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 513 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 514 issue is present in r0p0 as well but there is no workaround for that 515 revision. It is still open. 516 517- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 518 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 519 the CPU. 520 521- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 522 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 523 It has been fixed in r1p2. 524 525- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 526 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 527 It is still open. 528 529- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 530 CPU, this erratum affects system configurations that do not use an ARM 531 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 532 It has been fixed in r1p2. 533 534- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 535 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 536 CPU. It is still open. 537 538- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 539 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 540 CPU. It is still open. 541 542- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 543 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 544 CPU. It is still open. 545 546For Neoverse V2, the following errata build flags are defined : 547 548- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 549 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still 550 open. 551 552- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 553 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 554 r0p2. 555 556- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 557 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 558 r0p2. 559 560- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 561 CPU, this affects system configurations that do not use and ARM interconnect 562 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 563 in r0p2. 564 565- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 566 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 567 r0p2. 568 569- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 570 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 571 r0p2. 572 573- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 574 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 575 r0p2. 576 577- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 578 CPU, this affects all configurations. This needs to be enabled for revisions 579 r0p0 and r0p1. It has been fixed in r0p2. 580 581For Neoverse V3, the following errata build flags are defined : 582 583- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3 584 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 585 586- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3 587 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and 588 is still open. 589 590For Cortex-A710, the following errata build flags are defined : 591 592- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 593 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 594 r2p0 of the CPU. It is still open. 595 596- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 597 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 598 r2p0 of the CPU. It is still open. 599 600- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 601 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 602 and is still open. 603 604- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 605 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 606 of the CPU and is still open. 607 608- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 609 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 610 is still open. 611 612- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 613 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 614 and r2p1 of the CPU and is still open. 615 616- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 617 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 618 of the CPU and is fixed in r2p1. 619 620- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 621 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 622 of the CPU and is fixed in r2p1. 623 624- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 625 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 626 and is fixed in r2p1. 627 628- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 629 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 630 of the CPU and is fixed in r2p1. 631 632- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 633 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 634 r2p1 of the CPU and is still open. 635 636- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 637 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 638 of the CPU and is fixed in r2p1. 639 640- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 641 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 642 of the CPU and is fixed in r2p1. 643 644- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 645 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 646 of the CPU and is fixed in r2p1. 647 648- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 649 CPU, and applies to system configurations that do not use and ARM 650 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 651 is still open. 652 653- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 654 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 655 r2p1 of the CPU and is still open. 656 657- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 658 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 659 r2p1 of the CPU and is still open. 660 661- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 662 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 663 CPU and is still open. 664 665- ``ERRATA_A710_3701772``: This applies errata 3701772 workaround to Cortex-A710 666 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the 667 CPU and is still open. 668 669For Neoverse N2, the following errata build flags are defined : 670 671- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 672 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 673 674- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 675 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 676 677- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 678 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 679 680- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 681 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 682 683- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 684 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 685 686- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 687 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 688 689- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 690 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. 691 692- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 693 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 694 695- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 696 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 697 698- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 699 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 700 701- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 702 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 703 704- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 705 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 706 r0p1. 707 708- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 709 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 710 r0p1. 711 712- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 713 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 714 it is fixed in r0p3. 715 716- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 717 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 718 719- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 720 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 721 r0p1. 722 723- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 724 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 725 in r0p3. 726 727- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 728 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 729 in r0p3. 730 731- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 732 CPU, this erratum affects system configurations that do not use and ARM 733 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 734 It is fixed in r0p3. 735 736- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 737 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 738 in r0p3. 739 740- ``ERRATA_N2_3701773``: This applies errata 3701773 workaround to Neoverse-N2 741 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is 742 still open. 743 744For Neoverse N3, the following errata build flags are defined : 745 746- ``ERRATA_N3_3699563``: This applies errata 3699563 workaround to Neoverse-N3 747 CPU. This needs to be enabled for revisions r0p0 and is still open. 748 749For Cortex-X2, the following errata build flags are defined : 750 751- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 752 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 753 it is still open. 754 755- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 756 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU, 757 it is still open. 758 759- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 760 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 761 762- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 763 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 764 CPU, it is fixed in r2p1. 765 766- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 767 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 768 CPU, it is fixed in r2p1. 769 770- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 771 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 772 CPU, it is fixed in r2p1. 773 774- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 775 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 776 in r2p1. 777 778- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 779 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 780 CPU and is still open. 781 782- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 783 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU 784 and is fixed in r2p1. 785 786- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 787 CPU and affects system configurations that do not use an ARM interconnect IP. 788 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 789 still open. 790 791- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 792 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 793 CPU and is still open. 794 795- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 796 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 797 CPU and is still open. 798 799- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 800 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 801 CPU and it is still open. 802 803- ``ERRATA_X2_3701772``: This applies errata 3701772 workaround to Cortex-X2 804 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 805 CPU and it is still open. 806 807For Cortex-X3, the following errata build flags are defined : 808 809- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 810 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of 811 the CPU and is still open. 812 813- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 814 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 815 is fixed in r1p1. 816 817- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 818 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 819 fixed in r1p2. 820 821- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 822 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 823 of the CPU, it is fixed in r1p1. 824 825- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 826 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 827 of the CPU, it is fixed in r1p1. 828 829- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 830 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 831 CPU, it is fixed in r1p2. 832 833- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 834 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 835 It is fixed in r1p1. 836 837- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 838 CPU and affects system configurations that do not use an ARM interconnect 839 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 840 in r1p2. 841 842- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 843 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 844 r1p1. It is fixed in r1p2. 845 846- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 847 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 848 fixed in r1p2. 849 850- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 851 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 852 CPU. It is fixed in r1p2. 853 854- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3 855 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 856 of the CPU and it is still open. 857 858For Cortex-X4, the following errata build flags are defined : 859 860- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 861 CPU and affects system configurations that do not use an Arm interconnect IP. 862 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 863 The workaround for this erratum is not implemented in EL3, but the flag can 864 be enabled/disabled at the platform level. The flag is used when the errata ABI 865 feature is enabled and can assist the Kernel in the process of 866 mitigation of the erratum. 867 868- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 869 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 870 r0p2. 871 872- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 873 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 874 in r0p2. 875 876- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 877 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 878 879- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 880 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 881 882- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 883 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 884 885- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 886 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 887 888- ``ERRATA_X4_2957258``: This applies errata 2957258 workaround to Cortex-X4 889 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 890 891- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 892 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 893 894- ``ERRATA_X4_3701758``: This applies errata 3701758 workaround to Cortex-X4 895 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3. 896 It is still open. 897 898For Cortex-X925, the following errata build flags are defined : 899 900- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925 901 CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1. 902 903- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925 904 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open. 905 906For Cortex-A510, the following errata build flags are defined : 907 908- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 909 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 910 fixed in r0p1. 911 912- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 913 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 914 r0p2, r0p3 and r1p0, it is fixed in r1p1. 915 916- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 917 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 918 r0p2, it is fixed in r0p3. 919 920- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 921 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 922 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 923 workaround for those revisions. 924 925- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 926 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 927 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 928 workaround for those revisions. 929 930- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 931 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 932 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 933 ENABLE_MPMM=1. 934 935- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 936 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 937 r0p3 and r1p0, it is fixed in r1p1. 938 939- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 940 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 941 r0p3 and r1p0, it is fixed in r1p1. 942 943- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 944 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 945 r0p3, r1p0 and r1p1. It is fixed in r1p2. 946 947- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 948 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 949 r0p3, r1p0, r1p1, and is fixed in r1p2. 950 951- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 952 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 953 r0p3, r1p0, r1p1. It is fixed in r1p2. 954 955- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 956 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 957 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 958 959- ``ERRATA_A510_2971420``: This applies erratum 2971420 workaround to 960 Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3, 961 r1p0, r1p1, r1p2 and r1p3 and is still open. 962 963For Cortex-A520, the following errata build flags are defined : 964 965- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 966 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 967 CPU and is still open. 968 969- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 970 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 971 It is still open. 972 973- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 974 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 975 It is fixed in r0p2. 976 977For Cortex-A715, the following errata build flags are defined : 978 979- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 980 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 981 It is fixed in r1p1. 982 983- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 984 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 985 fixed in r1p1. 986 987- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 988 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 989 when SPE(Statistical profiling extension)=True. The errata is fixed 990 in r1p1. 991 992- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 993 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 994 It is fixed in r1p1. 995 996- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 997 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 998 workaround for revision r0p0. It is fixed in r1p1. 999 1000- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 1001 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 1002 It is fixed in r1p1. 1003 1004- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 1005 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 1006 and r1p1. It is fixed in r1p2. 1007 1008- ``ERRATA_A715_2804830``: This applies errata 2804830 workaround to 1009 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1010 r1p1 and r1p2. It is fixed in r1p3. 1011 1012- ``ERRATA_A715_3699560``: This applies errata 3699560 workaround to 1013 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0, 1014 r1p2 and r1p3. It is still open. 1015 1016For Cortex-A720, the following errata build flags are defined : 1017 1018- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 1019 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1020 It is fixed in r0p2. 1021 1022- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 1023 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1024 It is fixed in r0p2. 1025 1026- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 1027 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1028 It is fixed in r0p2. 1029 1030- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 1031 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1032 It is fixed in r0p2. 1033 1034- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to 1035 Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 1036 and r0p2. It is still open. 1037 1038For Cortex-A720_AE, the following errata build flags are defined : 1039 1040- ``ERRATA_A720_AE_3699562``: This applies errata 3699562 workaround 1041 to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0. 1042 It is still open. 1043 1044For Cortex-A725, the following errata build flags are defined : 1045 1046- ``ERRATA_A725_3699564``: This applies errata 3699564 workaround to 1047 Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1. 1048 It is fixed in r0p2. 1049 1050DSU Errata Workarounds 1051---------------------- 1052 1053Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 1054Shared Unit) errata. The DSU errata details can be found in the respective Arm 1055documentation: 1056 1057- `Arm DSU Software Developers Errata Notice`_. 1058 1059Each erratum is identified by an ``ID``, as defined in the DSU errata notice 1060document. Thus, the build flags which enable/disable the errata workarounds 1061have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 1062of DSU errata workarounds are similar to `CPU errata workarounds`_. 1063 1064For DSU errata, the following build flags are defined: 1065 1066- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 1067 affected DSU configurations. This errata applies only for those DSUs that 1068 revision is r0p0 (on r0p1 it is fixed). However, please note that this 1069 workaround results in increased DSU power consumption on idle. 1070 1071- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 1072 affected DSU configurations. This errata applies only for those DSUs that 1073 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1074 r2p0 it is fixed). However, please note that this workaround results in 1075 increased DSU power consumption on idle. 1076 1077- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1078 affected DSU configurations. This errata applies for those DSUs with 1079 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1080 please note that this workaround results in increased DSU power consumption 1081 on idle. 1082 1083CPU Specific optimizations 1084-------------------------- 1085 1086This section describes some of the optimizations allowed by the CPU micro 1087architecture that can be enabled by the platform as desired. 1088 1089- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1090 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1091 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1092 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1093 is a known safe deviation from the Cortex-A57 TRM defined power down 1094 sequence. Each Cortex-A57 based platform must make its own decision on 1095 whether to use the optimization. 1096 1097- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1098 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1099 in a way most programmers expect, and will most probably result in a 1100 significant speed degradation to any code that employs them. The Armv8-A 1101 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1102 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1103 flag enforces this behaviour. This needs to be enabled only for revisions 1104 <= r0p3 of the CPU and is enabled by default. 1105 1106- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1107 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1108 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1109 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1110 `Cortex-A57 Software Optimization Guide`_. 1111 1112- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1113 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1114 this bit only if their memory system meets the requirement that cache 1115 line fill requests from the Cortex-A57 processor are atomic. Each 1116 Cortex-A57 based platform must make its own decision on whether to use 1117 the optimization. This flag is disabled by default. 1118 1119- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1120 level cache(LLC) is present in the system, and that the DataSource field 1121 on the master CHI interface indicates when data is returned from the LLC. 1122 This is used to control how the LL_CACHE* PMU events count. 1123 Default value is 0 (Disabled). 1124 1125GIC Errata Workarounds 1126---------------------- 1127- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1128 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1129 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1130 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1131 then this flag is enabled; otherwise, it is 0 (Disabled). 1132 1133-------------- 1134 1135*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* 1136 1137.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1138.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1139.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1140.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 1141.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 1142.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 1143.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 1144.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 1145