1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <dsu_macros.S> 11#include <neoverse_n2.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_neoverse_n2_3701773 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30cpu_reset_prologue neoverse_n2 31 32workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 33 /* Apply instruction patching sequence */ 34 ldr x0,=0x6 35 msr S3_6_c15_c8_0,x0 36 ldr x0,=0xF3A08002 37 msr S3_6_c15_c8_2,x0 38 ldr x0,=0xFFF0F7FE 39 msr S3_6_c15_c8_3,x0 40 ldr x0,=0x40000001003ff 41 msr S3_6_c15_c8_1,x0 42 ldr x0,=0x7 43 msr S3_6_c15_c8_0,x0 44 ldr x0,=0xBF200000 45 msr S3_6_c15_c8_2,x0 46 ldr x0,=0xFFEF0000 47 msr S3_6_c15_c8_3,x0 48 ldr x0,=0x40000001003f3 49 msr S3_6_c15_c8_1,x0 50workaround_reset_end neoverse_n2, ERRATUM(2002655) 51 52check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) 53 54workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 55 /* Stash ERRSELR_EL1 in x2 */ 56 mrs x2, ERRSELR_EL1 57 58 /* Select error record 0 and clear ED bit */ 59 msr ERRSELR_EL1, xzr 60 mrs x1, ERXCTLR_EL1 61 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 62 msr ERXCTLR_EL1, x1 63 64 /* Restore ERRSELR_EL1 from x2 */ 65 msr ERRSELR_EL1, x2 66workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB 67 68check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) 69 70workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 71 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 72workaround_reset_end neoverse_n2, ERRATUM(2025414) 73 74check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) 75 76workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 77 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 78workaround_reset_end neoverse_n2, ERRATUM(2067956) 79 80check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) 81 82workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 83 /* Apply instruction patching sequence */ 84 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 85 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 86 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 87 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 88workaround_reset_end neoverse_n2, ERRATUM(2138953) 89 90check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) 91 92workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 93 /* Apply instruction patching sequence */ 94 ldr x0,=0x3 95 msr S3_6_c15_c8_0,x0 96 ldr x0,=0xF3A08002 97 msr S3_6_c15_c8_2,x0 98 ldr x0,=0xFFF0F7FE 99 msr S3_6_c15_c8_3,x0 100 ldr x0,=0x10002001003FF 101 msr S3_6_c15_c8_1,x0 102 ldr x0,=0x4 103 msr S3_6_c15_c8_0,x0 104 ldr x0,=0xBF200000 105 msr S3_6_c15_c8_2,x0 106 ldr x0,=0xFFEF0000 107 msr S3_6_c15_c8_3,x0 108 ldr x0,=0x10002001003F3 109 msr S3_6_c15_c8_1,x0 110workaround_reset_end neoverse_n2, ERRATUM(2138956) 111 112check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) 113 114 115workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 116 /* Apply instruction patching sequence */ 117 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 118workaround_reset_end neoverse_n2, ERRATUM(2138958) 119 120check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) 121 122workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 123 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 124workaround_reset_end neoverse_n2, ERRATUM(2189731) 125 126check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) 127 128workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 129 /* Apply instruction patching sequence */ 130 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 131 ldr x0, =0x2 132 msr S3_6_c15_c8_0, x0 133 ldr x0, =0x10F600E000 134 msr S3_6_c15_c8_2, x0 135 ldr x0, =0x10FF80E000 136 msr S3_6_c15_c8_3, x0 137 ldr x0, =0x80000000003FF 138 msr S3_6_c15_c8_1, x0 139workaround_reset_end neoverse_n2, ERRATUM(2242400) 140 141check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) 142 143workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 144 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 145workaround_reset_end neoverse_n2, ERRATUM(2242415) 146 147check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) 148 149workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 150 /* Apply instruction patching sequence */ 151 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 152workaround_reset_end neoverse_n2, ERRATUM(2280757) 153 154check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) 155 156workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941 157 errata_dsu_2313941_wa_impl 158workaround_reset_end neoverse_n2, ERRATUM(2313941) 159 160check_erratum_custom_start neoverse_n2, ERRATUM(2313941) 161 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 162 check_errata_dsu_2313941_impl 163 2: 164 ret 165check_erratum_custom_end neoverse_n2, ERRATUM(2313941) 166 167.global erratum_neoverse_n2_2326639_wa 168workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 169 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 170 * the workaround. Second call clears it to undo it. */ 171 sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 172workaround_runtime_end neoverse_n2, ERRATUM(2326639) 173 174check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) 175 176workaround_reset_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 177 /* Set bit 61 in CPUACTLR5_EL1 */ 178 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) 179workaround_reset_end neoverse_n2, ERRATUM(2340933) 180 181check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) 182 183workaround_reset_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 184 /* Set TXREQ to STATIC and full L2 TQ size */ 185 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 186 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL 187 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH 188 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 189workaround_reset_end neoverse_n2, ERRATUM(2346952) 190 191check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) 192 193workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 194 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM 195 * ST to behave like PLD/PFRM LD and not cause 196 * invalidations to other PE caches. 197 */ 198 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 199workaround_reset_end neoverse_n2, ERRATUM(2376738) 200 201check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) 202 203workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 204 /*Set bit 40 in ACTLR2_EL1 */ 205 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 206workaround_reset_end neoverse_n2, ERRATUM(2388450) 207 208check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) 209 210workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 211 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 212 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 213 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 214workaround_reset_end neoverse_n2, ERRATUM(2743014) 215 216check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) 217 218workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 219 /* dsb before isb of power down sequence */ 220 dsb sy 221workaround_runtime_end neoverse_n2, ERRATUM(2743089) 222 223check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) 224 225workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 226 /* Set bit 47 in ACTLR3_EL1 */ 227 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 228workaround_reset_end neoverse_n2, ERRATUM(2779511) 229 230check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) 231 232add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773 233 234check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3) 235 236workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 237#if IMAGE_BL31 238 /* 239 * The Neoverse-N2 generic vectors are overridden to apply errata 240 * mitigation on exception entry from lower ELs. 241 */ 242 override_vector_table wa_cve_vbar_neoverse_n2 243#endif /* IMAGE_BL31 */ 244workaround_reset_end neoverse_n2, CVE(2022,23960) 245 246check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 247 248/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 249workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 250 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46) 251workaround_reset_end neoverse_n2, CVE(2024, 5660) 252 253check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3) 254 255 /* ------------------------------------------- 256 * The CPU Ops reset function for Neoverse N2. 257 * ------------------------------------------- 258 */ 259cpu_reset_func_start neoverse_n2 260 261 /* Check if the PE implements SSBS */ 262 mrs x0, id_aa64pfr1_el1 263 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 264 b.eq 1f 265 266 /* Disable speculative loads */ 267 msr SSBS, xzr 2681: 269 /* Force all cacheable atomic instructions to be near */ 270 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 271 272#if ENABLE_FEAT_AMU 273 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 274 sysreg_bit_clear cptr_el3, TAM_BIT 275 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 276 sysreg_bit_clear cptr_el2, TAM_BIT 277 /* No need to enable the counters as this would be done at el3 exit */ 278#endif 279 280#if NEOVERSE_Nx_EXTERNAL_LLC 281 /* Some systems may have External LLC, core needs to be made aware */ 282 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 283#endif 284cpu_reset_func_end neoverse_n2 285 286func neoverse_n2_core_pwr_dwn 287 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV 288 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV 289 290 /* --------------------------------------------------- 291 * Enable CPU power down bit in power control register 292 * No need to do cache maintenance here. 293 * --------------------------------------------------- 294 */ 295 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT 296 297 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV 298 299 isb 300 ret 301endfunc neoverse_n2_core_pwr_dwn 302 303 /* --------------------------------------------- 304 * This function provides Neoverse N2 specific 305 * register information for crash reporting. 306 * It needs to return with x6 pointing to 307 * a list of register names in ASCII and 308 * x8 - x15 having values of registers to be 309 * reported. 310 * --------------------------------------------- 311 */ 312.section .rodata.neoverse_n2_regs, "aS" 313neoverse_n2_regs: /* The ASCII list of register names to be reported */ 314 .asciz "cpupwrctlr_el1", "" 315 316func neoverse_n2_cpu_reg_dump 317 adr x6, neoverse_n2_regs 318 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 319 ret 320endfunc neoverse_n2_cpu_reg_dump 321 322declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 323 neoverse_n2_reset_func, \ 324 neoverse_n2_core_pwr_dwn 325