1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <bl31/interrupt_mgmt.h>
15 #include <drivers/console.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17 #include <plat/common/platform.h>
18
19 #include <rpi_hw.h>
20 #include <rpi_shared.h>
21
22 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
23 DEVICE0_SIZE, \
24 MT_DEVICE | MT_RW | MT_SECURE)
25
26 #ifdef SHARED_RAM_BASE
27 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
28 SHARED_RAM_SIZE, \
29 MT_DEVICE | MT_RW | MT_SECURE)
30 #endif
31
32 #ifdef RPI3_PRELOADED_DTB_BASE
33 #define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \
34 MT_MEMORY | MT_RW | MT_NS)
35 #endif
36
37 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
38 MT_MEMORY | MT_RW | MT_NS)
39
40 #define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \
41 PLAT_RPI3_FIP_MAX_SIZE, \
42 MT_MEMORY | MT_RO | MT_NS)
43
44 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
45 MT_MEMORY | MT_RW | MT_SECURE)
46
47 #ifdef SPD_opteed
48 #define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
49 RPI3_OPTEE_PAGEABLE_LOAD_BASE, \
50 RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \
51 MT_MEMORY | MT_RW | MT_SECURE)
52 #endif
53
54 /*
55 * Table of regions for various BL stages to map using the MMU.
56 */
57 #ifdef IMAGE_BL1
58 static const mmap_region_t plat_rpi3_mmap[] = {
59 #ifdef MAP_SHARED_RAM
60 MAP_SHARED_RAM,
61 #endif
62 MAP_DEVICE0,
63 MAP_FIP,
64 #ifdef SPD_opteed
65 MAP_OPTEE_PAGEABLE,
66 #endif
67 {0}
68 };
69 #endif
70
71 #ifdef IMAGE_BL2
72 static const mmap_region_t plat_rpi3_mmap[] = {
73 #ifdef MAP_SHARED_RAM
74 MAP_SHARED_RAM,
75 #endif
76 MAP_DEVICE0,
77 MAP_FIP,
78 #if MEASURED_BOOT
79 RPI3_MAP_BL1_RW,
80 #endif
81 MAP_NS_DRAM0,
82 #ifdef BL32_BASE
83 MAP_BL32_MEM,
84 #endif
85 {0}
86 };
87 #endif
88
89 #ifdef IMAGE_BL31
90 static const mmap_region_t plat_rpi3_mmap[] = {
91 #ifdef MAP_SHARED_RAM
92 MAP_SHARED_RAM,
93 #endif
94 MAP_DEVICE0,
95 #ifdef RPI3_PRELOADED_DTB_BASE
96 MAP_NS_DTB,
97 #endif
98 #ifdef BL32_BASE
99 MAP_BL32_MEM,
100 #endif
101 {0}
102 };
103 #endif
104
105 /*******************************************************************************
106 * Function that sets up the console
107 ******************************************************************************/
108 static console_t rpi3_console;
109
rpi3_console_init(void)110 void rpi3_console_init(void)
111 {
112 int console_scope = CONSOLE_FLAG_BOOT;
113 int rc;
114
115 if (RPI3_RUNTIME_UART != -1)
116 console_scope |= CONSOLE_FLAG_RUNTIME;
117
118 rc = rpi3_register_used_uart(&rpi3_console);
119
120 if (rc == 0) {
121 /*
122 * The crash console doesn't use the multi console API, it uses
123 * the core console functions directly. It is safe to call panic
124 * and let it print debug information.
125 */
126 panic();
127 }
128
129 console_set_scope(&rpi3_console, console_scope);
130 }
131
132 /*******************************************************************************
133 * Function that sets up the translation tables.
134 ******************************************************************************/
rpi3_setup_page_tables(uintptr_t total_base,size_t total_size,uintptr_t code_start,uintptr_t code_limit,uintptr_t rodata_start,uintptr_t rodata_limit,uintptr_t coh_start,uintptr_t coh_limit)135 void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
136 uintptr_t code_start, uintptr_t code_limit,
137 uintptr_t rodata_start, uintptr_t rodata_limit
138 #if USE_COHERENT_MEM
139 , uintptr_t coh_start, uintptr_t coh_limit
140 #endif
141 )
142 {
143 /*
144 * Map the Trusted SRAM with appropriate memory attributes.
145 * Subsequent mappings will adjust the attributes for specific regions.
146 */
147 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
148 (void *) total_base, (void *) (total_base + total_size));
149 mmap_add_region(total_base, total_base,
150 total_size,
151 MT_MEMORY | MT_RW | MT_SECURE);
152
153 /* Re-map the code section */
154 VERBOSE("Code region: %p - %p\n",
155 (void *) code_start, (void *) code_limit);
156 mmap_add_region(code_start, code_start,
157 code_limit - code_start,
158 MT_CODE | MT_SECURE);
159
160 /* Re-map the read-only data section */
161 VERBOSE("Read-only data region: %p - %p\n",
162 (void *) rodata_start, (void *) rodata_limit);
163 mmap_add_region(rodata_start, rodata_start,
164 rodata_limit - rodata_start,
165 MT_RO_DATA | MT_SECURE);
166
167 #if USE_COHERENT_MEM
168 /* Re-map the coherent memory region */
169 VERBOSE("Coherent region: %p - %p\n",
170 (void *) coh_start, (void *) coh_limit);
171 mmap_add_region(coh_start, coh_start,
172 coh_limit - coh_start,
173 MT_DEVICE | MT_RW | MT_SECURE);
174 #endif
175
176 mmap_add(plat_rpi3_mmap);
177
178 init_xlat_tables();
179 }
180
181 /*******************************************************************************
182 * Gets SPSR for BL32 entry
183 ******************************************************************************/
rpi3_get_spsr_for_bl32_entry(void)184 uint32_t rpi3_get_spsr_for_bl32_entry(void)
185 {
186 /*
187 * The Secure Payload Dispatcher service is responsible for
188 * setting the SPSR prior to entry into the BL32 image.
189 */
190 return 0;
191 }
192
193 /*******************************************************************************
194 * Gets SPSR for BL33 entry
195 ******************************************************************************/
rpi3_get_spsr_for_bl33_entry(void)196 uint32_t rpi3_get_spsr_for_bl33_entry(void)
197 {
198 #if RPI3_BL33_IN_AARCH32
199 INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n");
200 return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE,
201 DISABLE_ALL_EXCEPTIONS);
202 #else
203 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
204 #endif
205 }
206
plat_get_syscnt_freq2(void)207 unsigned int plat_get_syscnt_freq2(void)
208 {
209 return SYS_COUNTER_FREQ_IN_TICKS;
210 }
211
plat_ic_get_pending_interrupt_type(void)212 uint32_t plat_ic_get_pending_interrupt_type(void)
213 {
214 ERROR("rpi3: Interrupt routed to EL3.\n");
215 return INTR_TYPE_INVAL;
216 }
217
plat_interrupt_type_to_line(uint32_t type,uint32_t security_state)218 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
219 {
220 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) ||
221 (type == INTR_TYPE_NS));
222
223 assert(sec_state_is_valid(security_state));
224
225 /* Non-secure interrupts are signalled on the IRQ line always. */
226 if (type == INTR_TYPE_NS)
227 return __builtin_ctz(SCR_IRQ_BIT);
228
229 /* Secure interrupts are signalled on the FIQ line always. */
230 return __builtin_ctz(SCR_FIQ_BIT);
231 }
232
233 #if MEASURED_BOOT || TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)234 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
235 {
236 return get_mbedtls_heap_helper(heap_addr, heap_size);
237 }
238 #endif
239