docs(per-cpu): clean up NUMA docs

This change incorporates resolutions for the remaining code review
comments on the NUMA documentation, which were intentionally left
unresolved when the NUMA stack

docs(per-cpu): clean up NUMA docs

This change incorporates resolutions for the remaining code review
comments on the NUMA documentation, which were intentionally left
unresolved when the NUMA stack was expedited.

Additionally, general improvements include:

- Documentation has been re-flowed with Pandoc;
- Diagram file-names follow naming conventions;
- Diagram alt-text better reflects the image content;
- Diagram widths scale with the content body width; and
- Grammar and spelling follow American English.

Change-Id: Ib172b554347caa8a72229081682b07fdb6417b64
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(cpufeat): mark RME_GDI, IDTE3 and RME_GPC2 as supported

Update architecture_features.rst to reflect that FEAT_RME_GDI,
FEAT_IDTE3, and FEAT_RME_GPC2 are now marked as OK instead of WIP.

Signed

docs(cpufeat): mark RME_GDI, IDTE3 and RME_GPC2 as supported

Update architecture_features.rst to reflect that FEAT_RME_GDI,
FEAT_IDTE3, and FEAT_RME_GPC2 are now marked as OK instead of WIP.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I27cfd01657fe6df4b0a4e4551f120dd279830213

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docs(juno): update PSCI instrumentation data

Update for v2.14 release based on v2.14-rc0

Change-Id: Id0cf75e284cc02a513d134ccd550fe9a73ac6909
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

feat(docs): document PSCI power_state

Add reference to the ARM PSCI spec which provides details about the
power_state.
Document about the EXTENDED_STATE_ID too since some users may
require it, but m

feat(docs): document PSCI power_state

Add reference to the ARM PSCI spec which provides details about the
power_state.
Document about the EXTENDED_STATE_ID too since some users may
require it, but may not be aware of how to enable it.
Along with this, add couple of lines to describe how TF-A PSCI
framework does some level of sanity validation of this state.

Change-Id: I1f37eab957549c47b500c9592ecf4c9814b6cf2a
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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docs(ff-a): document `sri-interrupts-policy` field

Add the encoding information for the `sri-interrupts-policy` field
for SP FF-A manifest.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ib

docs(ff-a): document `sri-interrupts-policy` field

Add the encoding information for the `sri-interrupts-policy` field
for SP FF-A manifest.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ib8f6a3ba02be3a312abd1f8ab4a75874290a244f

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docs: describe RAS KFH limitations and its mitigation in future

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I27b739413140fc310b2bcb3a0812e07ba29e36d8

Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register def

Merge changes from topic "ar/idte3" into integration

* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register defines and read helpers

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Merge "docs(cpufeat): add a checklist on how to add a feature" into integration

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t

feat(cpufeat): add support for FEAT_IDTE3

This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.

The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.

The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.

FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.

This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.

This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5

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docs(maintainers): add per-cpu framework into maintainers.rst

Add Rohit Mathew <rohit.mathew@arm.com> and Sammit Joshi
<sammit.joshi@arm.com> as code owners for the per-CPU framework.

Add Manish Pa

docs(maintainers): add per-cpu framework into maintainers.rst

Add Rohit Mathew <rohit.mathew@arm.com> and Sammit Joshi
<sammit.joshi@arm.com> as code owners for the per-CPU framework.

Add Manish Pandey <manish.pandey2@arm.com> and
Chris Kay <chris.kay@arm.com> as a code owner alongside
the authors.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: If81e097d8b52d083cff9e0722c5550322cffd245

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feat(per-cpu): add documentation for per-cpu framework

add documentation for numa aware per-cpu framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Sammit Joshi <sammit.jos

feat(per-cpu): add documentation for per-cpu framework

add documentation for numa aware per-cpu framework.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ibd39adea95aa24abb588ff518547bdc1ec46b0fe

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feat(per-cpu): migrate spm_core_context to per-cpu framework

migrate spm_core_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed

feat(per-cpu): migrate spm_core_context to per-cpu framework

migrate spm_core_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie600ae755cfb738adde51cfc4af3cddbbccbbaef

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feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-of

feat(per-cpu): migrate psci_ns_context to per-cpu framework

migrate psci_ns_context object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Change-Id: Ie8b9f4eea8c61d4de9996d9370634cbd08ff1d8d

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feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signe

feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework

migrate psci_cpu_pd_nodes object to the NUMA-aware per-cpu
framework to optimize memory access and to efficiently
utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idec3e3b74ecf03b420b339a183be2b9e00f8a78f

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feat(per-cpu): migrate rmm_context to per-cpu framework

migrate rmm_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: S

feat(per-cpu): migrate rmm_context to per-cpu framework

migrate rmm_context objects to the NUMA-aware per-cpu framework to
optimize memory access and to efficiently utilize memory.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I72d49c3d860dac10bd3930ce400b0199bedd887b

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docs(cpufeat): add a checklist on how to add a feature

Adding features is an arcane job with a long list of things to consider.
There is no single place to list these things so someone new to this
m

docs(cpufeat): add a checklist on how to add a feature

Adding features is an arcane job with a long list of things to consider.
There is no single place to list these things so someone new to this
must be guided along, usually at code review. Further, the process
changes occasionally so it can be difficult even for an experienced
contributor to get right.

So add a checklist along with brief explanations on what to look for so
we can make our job nicer.

Change-Id: I09dd0062b742c9fce5a8f86a2067adc941db6899
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from diffe

feat(lfa): introduce support for call_again for LFA_PRIME

LFA_PRIME is a single-threaded operation that is not pinned to
a specific CPU. The implementation must support calls being
issued from different CPUs, even for several calls to prime the
same component.

This patch checks if the plat_lfa_load_auth_image return -EAGAIN
indicating that the platform expects the LFA_PRIME call to be
issued again. This is done by returning LFA_SUCCESS and setting
flags[0] to 1, indicating that LFA_PRIME is incomplete and must
be called again.

Change-Id: Ia3046b5467c50c4c51392bac3fb9e9533f2438db
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio

Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot

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Merge changes Iad149a2c,Idcd2a07d,Id9429831 into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 3711916
fix(cpus): workaround for Cortex-A715 erratum 2376701
fix(cpus): w

Merge changes Iad149a2c,Idcd2a07d,Id9429831 into integration

* changes:
fix(cpus): workaround for Cortex-A715 erratum 3711916
fix(cpus): workaround for Cortex-A715 erratum 2376701
fix(cpus): workaround for Cortex-A715 erratum 2409570

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fix(cpus): workaround for Cortex-A715 erratum 3711916

Cortex-A715 erratum 3711916 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

SDEN documentation

fix(cpus): workaround for Cortex-A715 erratum 3711916

Cortex-A715 erratum 3711916 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, r1p2 and r1p3, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Iad149a2c02a804b3f4f0f2f5b89e866675cb4093
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2376701

Cortex-A715 erratum 2376701 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround is not expected t

fix(cpus): workaround for Cortex-A715 erratum 2376701

Cortex-A715 erratum 2376701 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround is not expected to have a significant performance
impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Idcd2a07d269d55534dc5faa59c454d37426f2cfa
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2409570

Cortex-A715 erratum 2409570 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround could have a sign

fix(cpus): workaround for Cortex-A715 erratum 2409570

Cortex-A715 erratum 2409570 is a Cat B erratum that applies to
revisions r0p0 and r1p0, and is fixed in r1p1.

This workaround could have a significant performance impact for
software that relies heavily on using store-release instructions.

This workaround only applies to r1p0, r0p0 has a different
workaround but is not used in production hardware so has not been
implemented.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827

Change-Id: Id9429831525b842779d7b7e60f103c93be4acd67
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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feat(cpus): add support for Neoverse-N2 prefetcher

To get accurate and repeatable L2 cache performance metrics,
the L2 region prefetcher must be disabled. This prevents
speculative fetches from inte

feat(cpus): add support for Neoverse-N2 prefetcher

To get accurate and repeatable L2 cache performance metrics,
the L2 region prefetcher must be disabled. This prevents
speculative fetches from interfering with the measurements.

This patch adds a build-time option, NEOVERSE_N2_PREFETCHER_DISABLE,
to set the PF_DIS bit (bit 15) in the CPUECTLR_EL1 register for this
purpose.

Change-Id: Ie7ab9e84bb29d042d0bb2ec697e0c1e39ad5032e
Signed-off-by: Rohit Ner <rohitner@google.com>

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Merge "docs: deprecate Arm RD1AE platform" into integration