1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Encodings for GICv5 EL3 system registers 95 ******************************************************************************/ 96 #define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4 97 #define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5 98 #define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6 99 #define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7 100 101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3) 102 #define ICC_PPI_DOMAINR_COUNT (32) 103 104 /******************************************************************************* 105 * Definitions for CPU system register interface to GICv3 106 ******************************************************************************/ 107 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 108 #define ICC_SGI1R S3_0_C12_C11_5 109 #define ICC_ASGI1R S3_0_C12_C11_6 110 #define ICC_SRE_EL1 S3_0_C12_C12_5 111 #define ICC_SRE_EL2 S3_4_C12_C9_5 112 #define ICC_SRE_EL3 S3_6_C12_C12_5 113 #define ICC_CTLR_EL1 S3_0_C12_C12_4 114 #define ICC_CTLR_EL3 S3_6_C12_C12_4 115 #define ICC_PMR_EL1 S3_0_C4_C6_0 116 #define ICC_RPR_EL1 S3_0_C12_C11_3 117 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 118 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 119 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 120 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 121 #define ICC_IAR0_EL1 S3_0_c12_c8_0 122 #define ICC_IAR1_EL1 S3_0_c12_c12_0 123 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 124 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 125 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 126 127 /******************************************************************************* 128 * Definitions for EL2 system registers for save/restore routine 129 ******************************************************************************/ 130 #define CNTPOFF_EL2 S3_4_C14_C0_6 131 #define HDFGRTR2_EL2 S3_4_C3_C1_0 132 #define HDFGWTR2_EL2 S3_4_C3_C1_1 133 #define HFGRTR2_EL2 S3_4_C3_C1_2 134 #define HFGWTR2_EL2 S3_4_C3_C1_3 135 #define HDFGRTR_EL2 S3_4_C3_C1_4 136 #define HDFGWTR_EL2 S3_4_C3_C1_5 137 #define HAFGRTR_EL2 S3_4_C3_C1_6 138 #define HFGITR2_EL2 S3_4_C3_C1_7 139 #define HFGITR_EL2 S3_4_C1_C1_6 140 #define HFGRTR_EL2 S3_4_C1_C1_4 141 #define HFGWTR_EL2 S3_4_C1_C1_5 142 #define ICH_HCR_EL2 S3_4_C12_C11_0 143 #define ICH_VMCR_EL2 S3_4_C12_C11_7 144 #define MPAMVPM0_EL2 S3_4_C10_C6_0 145 #define MPAMVPM1_EL2 S3_4_C10_C6_1 146 #define MPAMVPM2_EL2 S3_4_C10_C6_2 147 #define MPAMVPM3_EL2 S3_4_C10_C6_3 148 #define MPAMVPM4_EL2 S3_4_C10_C6_4 149 #define MPAMVPM5_EL2 S3_4_C10_C6_5 150 #define MPAMVPM6_EL2 S3_4_C10_C6_6 151 #define MPAMVPM7_EL2 S3_4_C10_C6_7 152 #define MPAMVPMV_EL2 S3_4_C10_C4_1 153 #define VNCR_EL2 S3_4_C2_C2_0 154 #define PMSCR_EL2 S3_4_C9_C9_0 155 #define TFSR_EL2 S3_4_C5_C6_0 156 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 157 #define TTBR1_EL2 S3_4_C2_C0_1 158 159 /******************************************************************************* 160 * Generic timer memory mapped registers & offsets 161 ******************************************************************************/ 162 #define CNTCR_OFF U(0x000) 163 #define CNTCV_OFF U(0x008) 164 #define CNTFID_OFF U(0x020) 165 166 #define CNTCR_EN (U(1) << 0) 167 #define CNTCR_HDBG (U(1) << 1) 168 #define CNTCR_FCREQ(x) ((x) << 8) 169 170 /******************************************************************************* 171 * System register bit definitions 172 ******************************************************************************/ 173 /* CLIDR definitions */ 174 #define LOUIS_SHIFT U(21) 175 #define LOC_SHIFT U(24) 176 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 177 #define CLIDR_FIELD_WIDTH U(3) 178 179 /* CSSELR definitions */ 180 #define LEVEL_SHIFT U(1) 181 182 /* Data cache set/way op type defines */ 183 #define DCISW U(0x0) 184 #define DCCISW U(0x1) 185 #if ERRATA_A53_827319 186 #define DCCSW DCCISW 187 #else 188 #define DCCSW U(0x2) 189 #endif 190 191 #define ID_REG_FIELD_MASK ULL(0xf) 192 193 /* ID_AA64PFR0_EL1 definitions */ 194 #define ID_AA64PFR0_EL0_SHIFT U(0) 195 #define ID_AA64PFR0_EL1_SHIFT U(4) 196 #define ID_AA64PFR0_EL2_SHIFT U(8) 197 #define ID_AA64PFR0_EL3_SHIFT U(12) 198 199 #define ID_AA64PFR0_AMU_SHIFT U(44) 200 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 201 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 202 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 203 204 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 205 206 #define ID_AA64PFR0_GIC_SHIFT U(24) 207 #define ID_AA64PFR0_GIC_WIDTH U(4) 208 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 209 210 #define ID_AA64PFR0_SVE_SHIFT U(32) 211 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 212 #define ID_AA64PFR0_SVE_LENGTH U(4) 213 #define SVE_IMPLEMENTED ULL(0x1) 214 215 #define ID_AA64PFR0_SEL2_SHIFT U(36) 216 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 217 218 #define ID_AA64PFR0_MPAM_SHIFT U(40) 219 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 220 221 #define ID_AA64PFR0_DIT_SHIFT U(48) 222 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 223 #define ID_AA64PFR0_DIT_LENGTH U(4) 224 #define DIT_IMPLEMENTED ULL(1) 225 226 #define ID_AA64PFR0_CSV2_SHIFT U(56) 227 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 228 #define ID_AA64PFR0_CSV2_LENGTH U(4) 229 #define CSV2_2_IMPLEMENTED ULL(0x2) 230 #define CSV2_3_IMPLEMENTED ULL(0x3) 231 232 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 233 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 234 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 235 #define RME_NOT_IMPLEMENTED ULL(0) 236 237 #define ID_AA64PFR0_RAS_SHIFT U(28) 238 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 239 #define ID_AA64PFR0_RAS_LENGTH U(4) 240 241 /* Exception level handling */ 242 #define EL_IMPL_NONE ULL(0) 243 #define EL_IMPL_A64ONLY ULL(1) 244 #define EL_IMPL_A64_A32 ULL(2) 245 246 /* ID_AA64DFR0_EL1.DebugVer definitions */ 247 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 248 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 249 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 250 251 /* ID_AA64DFR0_EL1.TraceVer definitions */ 252 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 253 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 254 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 255 256 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 257 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 258 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 259 #define TRACEFILT_IMPLEMENTED ULL(1) 260 261 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 262 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 263 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 264 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 265 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9) 266 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 267 268 /* ID_AA64DFR0_EL1.SEBEP definitions */ 269 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 270 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 271 #define SEBEP_IMPLEMENTED ULL(1) 272 273 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 274 #define ID_AA64DFR0_PMS_SHIFT U(32) 275 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 276 #define SPE_IMPLEMENTED ULL(0x1) 277 #define SPE_NOT_IMPLEMENTED ULL(0x0) 278 279 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 280 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 281 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 282 #define TRACEBUFFER_IMPLEMENTED ULL(1) 283 284 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 285 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 286 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 287 #define MTPMU_IMPLEMENTED ULL(1) 288 #define MTPMU_NOT_IMPLEMENTED ULL(15) 289 290 /* ID_AA64DFR0_EL1.BRBE definitions */ 291 #define ID_AA64DFR0_BRBE_SHIFT U(52) 292 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 293 #define BRBE_IMPLEMENTED ULL(1) 294 295 /* ID_AA64DFR1_EL1 definitions */ 296 #define ID_AA64DFR1_EBEP_SHIFT U(48) 297 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 298 #define EBEP_IMPLEMENTED ULL(1) 299 300 /* ID_AA64ISAR0_EL1 definitions */ 301 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 302 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 303 304 /* ID_AA64ISAR1_EL1 definitions */ 305 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 306 307 #define ID_AA64ISAR1_LS64_SHIFT U(60) 308 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 309 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 310 #define LS64_V_IMPLEMENTED ULL(0x2) 311 #define LS64_IMPLEMENTED ULL(0x1) 312 #define LS64_NOT_IMPLEMENTED ULL(0x0) 313 314 #define ID_AA64ISAR1_SB_SHIFT U(36) 315 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 316 #define SB_IMPLEMENTED ULL(0x1) 317 #define SB_NOT_IMPLEMENTED ULL(0x0) 318 319 #define ID_AA64ISAR1_GPI_SHIFT U(28) 320 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 321 #define ID_AA64ISAR1_GPA_SHIFT U(24) 322 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 323 324 #define ID_AA64ISAR1_API_SHIFT U(8) 325 #define ID_AA64ISAR1_API_MASK ULL(0xf) 326 #define ID_AA64ISAR1_APA_SHIFT U(4) 327 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 328 329 /* ID_AA64ISAR2_EL1 definitions */ 330 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 331 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 332 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 333 334 #define MOPS_IMPLEMENTED ULL(0x1) 335 336 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 337 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 338 339 #define ID_AA64ISAR2_APA3_SHIFT U(12) 340 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 341 342 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 343 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 344 345 /* ID_AA64MMFR0_EL1 definitions */ 346 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 347 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 348 349 #define PARANGE_0000 U(32) 350 #define PARANGE_0001 U(36) 351 #define PARANGE_0010 U(40) 352 #define PARANGE_0011 U(42) 353 #define PARANGE_0100 U(44) 354 #define PARANGE_0101 U(48) 355 #define PARANGE_0110 U(52) 356 #define PARANGE_0111 U(56) 357 358 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 359 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 360 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 361 #define ECV_IMPLEMENTED ULL(0x1) 362 363 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 364 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 365 #define FGT2_IMPLEMENTED ULL(0x2) 366 #define FGT_IMPLEMENTED ULL(0x1) 367 #define FGT_NOT_IMPLEMENTED ULL(0x0) 368 369 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 370 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 371 372 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 373 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 374 375 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 376 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 377 #define TGRAN16_IMPLEMENTED ULL(0x1) 378 379 /* ID_AA64MMFR1_EL1 definitions */ 380 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 381 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 382 #define TWED_IMPLEMENTED ULL(0x1) 383 384 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 385 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 386 #define PAN_IMPLEMENTED ULL(0x1) 387 #define PAN2_IMPLEMENTED ULL(0x2) 388 #define PAN3_IMPLEMENTED ULL(0x3) 389 390 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 391 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 392 393 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 394 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 395 #define HCX_IMPLEMENTED ULL(0x1) 396 397 /* ID_AA64MMFR2_EL1 definitions */ 398 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 399 400 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 401 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 402 403 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 404 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 405 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 406 407 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 408 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 409 410 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 411 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 412 413 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 414 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 415 #define NV2_IMPLEMENTED ULL(0x2) 416 417 /* ID_AA64MMFR3_EL1 definitions */ 418 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 419 420 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 421 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 422 #define D128_IMPLEMENTED ULL(0x1) 423 424 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28) 425 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf) 426 427 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 428 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 429 430 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 431 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 432 433 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 434 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 435 436 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 437 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 438 439 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 440 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 441 #define SCTLR2_IMPLEMENTED ULL(1) 442 443 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 444 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 445 446 /* ID_AA64MMFR4_EL1 definitions */ 447 #define ID_AA64MMFR4_EL1 S3_0_C0_C7_4 448 449 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16) 450 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf) 451 #define FGWTE3_IMPLEMENTED ULL(0x1) 452 453 /* ID_AA64PFR1_EL1 definitions */ 454 455 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 456 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 457 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 458 459 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 460 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 461 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 462 463 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 464 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 465 466 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 467 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 468 469 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 470 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 471 #define NMI_IMPLEMENTED ULL(1) 472 473 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 474 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 475 #define GCS_IMPLEMENTED ULL(1) 476 477 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 478 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 479 #define THE_IMPLEMENTED ULL(1) 480 481 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 482 483 /* ID_AA64PFR2_EL1 definitions */ 484 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 485 486 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 487 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 488 489 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 490 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 491 492 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 493 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 494 495 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 496 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 497 498 #define FPMR_IMPLEMENTED ULL(0x1) 499 500 #define VDISR_EL2 S3_4_C12_C1_1 501 #define VSESR_EL2 S3_4_C5_C2_3 502 503 /* Memory Tagging Extension is not implemented */ 504 #define MTE_UNIMPLEMENTED U(0) 505 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 506 #define MTE_IMPLEMENTED_EL0 U(1) 507 /* FEAT_MTE2: Full MTE is implemented */ 508 #define MTE_IMPLEMENTED_ELX U(2) 509 /* 510 * FEAT_MTE3: MTE is implemented with support for 511 * asymmetric Tag Check Fault handling 512 */ 513 #define MTE_IMPLEMENTED_ASY U(3) 514 515 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 516 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 517 518 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 519 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 520 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 521 #define SME_IMPLEMENTED ULL(0x1) 522 #define SME2_IMPLEMENTED ULL(0x2) 523 #define SME_NOT_IMPLEMENTED ULL(0x0) 524 525 /* ID_AA64PFR2_EL1 definitions */ 526 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 527 #define ID_AA64PFR2_EL1_GCIE_SHIFT 12 528 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf) 529 530 /* ID_PFR1_EL1 definitions */ 531 #define ID_PFR1_VIRTEXT_SHIFT U(12) 532 #define ID_PFR1_VIRTEXT_MASK U(0xf) 533 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 534 & ID_PFR1_VIRTEXT_MASK) 535 536 /* SCTLR definitions */ 537 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 538 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 539 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 540 541 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 542 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 543 544 #define SCTLR_AARCH32_EL1_RES1 \ 545 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 546 (U(1) << 4) | (U(1) << 3)) 547 548 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 549 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 550 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 551 552 #define SCTLR_M_BIT (ULL(1) << 0) 553 #define SCTLR_A_BIT (ULL(1) << 1) 554 #define SCTLR_C_BIT (ULL(1) << 2) 555 #define SCTLR_SA_BIT (ULL(1) << 3) 556 #define SCTLR_SA0_BIT (ULL(1) << 4) 557 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 558 #define SCTLR_nAA_BIT (ULL(1) << 6) 559 #define SCTLR_ITD_BIT (ULL(1) << 7) 560 #define SCTLR_SED_BIT (ULL(1) << 8) 561 #define SCTLR_UMA_BIT (ULL(1) << 9) 562 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 563 #define SCTLR_EOS_BIT (ULL(1) << 11) 564 #define SCTLR_I_BIT (ULL(1) << 12) 565 #define SCTLR_EnDB_BIT (ULL(1) << 13) 566 #define SCTLR_DZE_BIT (ULL(1) << 14) 567 #define SCTLR_UCT_BIT (ULL(1) << 15) 568 #define SCTLR_NTWI_BIT (ULL(1) << 16) 569 #define SCTLR_NTWE_BIT (ULL(1) << 18) 570 #define SCTLR_WXN_BIT (ULL(1) << 19) 571 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 572 #define SCTLR_IESB_BIT (ULL(1) << 21) 573 #define SCTLR_EIS_BIT (ULL(1) << 22) 574 #define SCTLR_SPAN_BIT (ULL(1) << 23) 575 #define SCTLR_E0E_BIT (ULL(1) << 24) 576 #define SCTLR_EE_BIT (ULL(1) << 25) 577 #define SCTLR_UCI_BIT (ULL(1) << 26) 578 #define SCTLR_EnDA_BIT (ULL(1) << 27) 579 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 580 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 581 #define SCTLR_EnIB_BIT (ULL(1) << 30) 582 #define SCTLR_EnIA_BIT (ULL(1) << 31) 583 #define SCTLR_BT0_BIT (ULL(1) << 35) 584 #define SCTLR_BT1_BIT (ULL(1) << 36) 585 #define SCTLR_BT_BIT (ULL(1) << 36) 586 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 587 #define SCTLR_TCF0_SHIFT U(38) 588 #define SCTLR_TCF0_MASK ULL(3) 589 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 590 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 591 592 /* Tag Check Faults in EL0 have no effect on the PE */ 593 #define SCTLR_TCF0_NO_EFFECT U(0) 594 /* Tag Check Faults in EL0 cause a synchronous exception */ 595 #define SCTLR_TCF0_SYNC U(1) 596 /* Tag Check Faults in EL0 are asynchronously accumulated */ 597 #define SCTLR_TCF0_ASYNC U(2) 598 /* 599 * Tag Check Faults in EL0 cause a synchronous exception on reads, 600 * and are asynchronously accumulated on writes 601 */ 602 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 603 604 #define SCTLR_TCF_SHIFT U(40) 605 #define SCTLR_TCF_MASK ULL(3) 606 607 /* Tag Check Faults in EL1 have no effect on the PE */ 608 #define SCTLR_TCF_NO_EFFECT U(0) 609 /* Tag Check Faults in EL1 cause a synchronous exception */ 610 #define SCTLR_TCF_SYNC U(1) 611 /* Tag Check Faults in EL1 are asynchronously accumulated */ 612 #define SCTLR_TCF_ASYNC U(2) 613 /* 614 * Tag Check Faults in EL1 cause a synchronous exception on reads, 615 * and are asynchronously accumulated on writes 616 */ 617 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 618 619 #define SCTLR_ATA0_BIT (ULL(1) << 42) 620 #define SCTLR_ATA_BIT (ULL(1) << 43) 621 #define SCTLR_DSSBS_SHIFT U(44) 622 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 623 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 624 #define SCTLR_TWEDEL_SHIFT U(46) 625 #define SCTLR_TWEDEL_MASK ULL(0xf) 626 #define SCTLR_EnASR_BIT (ULL(1) << 54) 627 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 628 #define SCTLR_EnALS_BIT (ULL(1) << 56) 629 #define SCTLR_EPAN_BIT (ULL(1) << 57) 630 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 631 632 #define SCTLR2_EnPACM_BIT (ULL(1) << 7) 633 634 /* SCTLR2 currently has no RES1 fields so reset to 0 */ 635 #define SCTLR2_RESET_VAL ULL(0) 636 637 /* CPACR_EL1 definitions */ 638 #define CPACR_EL1_FPEN(x) ((x) << 20) 639 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 640 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 641 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 642 #define CPACR_EL1_SMEN_SHIFT U(24) 643 #define CPACR_EL1_SMEN_MASK ULL(0x3) 644 645 /* SCR definitions */ 646 #if ENABLE_FEAT_GCIE 647 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT) 648 #else 649 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 650 #endif 651 #define SCR_NSE_SHIFT U(62) 652 #define SCR_FGTEN2_BIT (UL(1) << 59) 653 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 654 #define SCR_EnFPM_BIT (ULL(1) << 50) 655 #define SCR_MECEn_BIT (UL(1) << 49) 656 #define SCR_GPF_BIT (UL(1) << 48) 657 #define SCR_D128En_BIT (UL(1) << 47) 658 #define SCR_TWEDEL_SHIFT U(30) 659 #define SCR_TWEDEL_MASK ULL(0xf) 660 #define SCR_PIEN_BIT (UL(1) << 45) 661 #define SCR_SCTLR2En_BIT (UL(1) << 44) 662 #define SCR_TCR2EN_BIT (UL(1) << 43) 663 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 664 #define SCR_ENTP2_SHIFT U(41) 665 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 666 #define SCR_TRNDR_BIT (UL(1) << 40) 667 #define SCR_GCSEn_BIT (UL(1) << 39) 668 #define SCR_HXEn_BIT (UL(1) << 38) 669 #define SCR_ADEn_BIT (UL(1) << 37) 670 #define SCR_EnAS0_BIT (UL(1) << 36) 671 #define SCR_AMVOFFEN_SHIFT U(35) 672 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 673 #define SCR_TWEDEn_BIT (UL(1) << 29) 674 #define SCR_ECVEN_BIT (UL(1) << 28) 675 #define SCR_FGTEN_BIT (UL(1) << 27) 676 #define SCR_ATA_BIT (UL(1) << 26) 677 #define SCR_EnSCXT_BIT (UL(1) << 25) 678 #define SCR_FIEN_BIT (UL(1) << 21) 679 #define SCR_EEL2_BIT (UL(1) << 18) 680 #define SCR_API_BIT (UL(1) << 17) 681 #define SCR_APK_BIT (UL(1) << 16) 682 #define SCR_TERR_BIT (UL(1) << 15) 683 #define SCR_TWE_BIT (UL(1) << 13) 684 #define SCR_TWI_BIT (UL(1) << 12) 685 #define SCR_ST_BIT (UL(1) << 11) 686 #define SCR_RW_BIT (UL(1) << 10) 687 #define SCR_SIF_BIT (UL(1) << 9) 688 #define SCR_HCE_BIT (UL(1) << 8) 689 #define SCR_SMD_BIT (UL(1) << 7) 690 #define SCR_EA_BIT (UL(1) << 3) 691 #define SCR_FIQ_BIT (UL(1) << 2) 692 #define SCR_IRQ_BIT (UL(1) << 1) 693 #define SCR_NS_BIT (UL(1) << 0) 694 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 695 #define SCR_RESET_VAL SCR_RES1_BITS 696 697 /* MDCR_EL3 definitions */ 698 #define MDCR_EBWE_BIT (ULL(1) << 43) 699 #define MDCR_EnPMS3_BIT (ULL(1) << 42) 700 #define MDCR_E3BREC_BIT (ULL(1) << 38) 701 #define MDCR_E3BREW_BIT (ULL(1) << 37) 702 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 703 #define MDCR_MPMX_BIT (ULL(1) << 35) 704 #define MDCR_MCCD_BIT (ULL(1) << 34) 705 #define MDCR_SBRBE_SHIFT U(32) 706 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 707 #define MDCR_SBRBE_ALL ULL(0x3) 708 #define MDCR_SBRBE_NS ULL(0x1) 709 #define MDCR_NSTB_EN_BIT (ULL(1) << 24) 710 #define MDCR_NSTB_SS_BIT (ULL(1) << 25) 711 #define MDCR_NSTBE_BIT (ULL(1) << 26) 712 #define MDCR_MTPME_BIT (ULL(1) << 28) 713 #define MDCR_TDCC_BIT (ULL(1) << 27) 714 #define MDCR_SCCD_BIT (ULL(1) << 23) 715 #define MDCR_EPMAD_BIT (ULL(1) << 21) 716 #define MDCR_EDAD_BIT (ULL(1) << 20) 717 #define MDCR_TTRF_BIT (ULL(1) << 19) 718 #define MDCR_STE_BIT (ULL(1) << 18) 719 #define MDCR_SPME_BIT (ULL(1) << 17) 720 #define MDCR_SDD_BIT (ULL(1) << 16) 721 #define MDCR_SPD32(x) ((x) << 14) 722 #define MDCR_SPD32_LEGACY ULL(0x0) 723 #define MDCR_SPD32_DISABLE ULL(0x2) 724 #define MDCR_SPD32_ENABLE ULL(0x3) 725 #define MDCR_NSPB_SS_BIT (ULL(1) << 13) 726 #define MDCR_NSPB_EN_BIT (ULL(1) << 12) 727 #define MDCR_NSPBE_BIT (ULL(1) << 11) 728 #define MDCR_TDOSA_BIT (ULL(1) << 10) 729 #define MDCR_TDA_BIT (ULL(1) << 9) 730 #define MDCR_EnPM2_BIT (ULL(1) << 7) 731 #define MDCR_TPM_BIT (ULL(1) << 6) 732 #define MDCR_RLTE_BIT (ULL(1) << 0) 733 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 734 735 /* MDCR_EL2 definitions */ 736 #define MDCR_EL2_MTPME (ULL(1) << 28) 737 #define MDCR_EL2_HLP_BIT (ULL(1) << 26) 738 #define MDCR_EL2_E2TB(x) ULL((x) << 24) 739 #define MDCR_EL2_E2TB_EL1 ULL(0x3) 740 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23) 741 #define MDCR_EL2_TTRF (ULL(1) << 19) 742 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17) 743 #define MDCR_EL2_TPMS (ULL(1) << 14) 744 #define MDCR_EL2_E2PB(x) ULL((x) << 12) 745 #define MDCR_EL2_E2PB_EL1 ULL(0x3) 746 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11) 747 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10) 748 #define MDCR_EL2_TDA_BIT (ULL(1) << 9) 749 #define MDCR_EL2_TDE_BIT (ULL(1) << 8) 750 #define MDCR_EL2_HPME_BIT (ULL(1) << 7) 751 #define MDCR_EL2_TPM_BIT (ULL(1) << 6) 752 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5) 753 #define MDCR_EL2_HPMN_MASK ULL(0x1f) 754 #define MDCR_EL2_RESET_VAL ULL(0x0) 755 756 /* HSTR_EL2 definitions */ 757 #define HSTR_EL2_RESET_VAL U(0x0) 758 #define HSTR_EL2_T_MASK U(0xff) 759 760 /* CNTHP_CTL_EL2 definitions */ 761 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 762 #define CNTHP_CTL_RESET_VAL U(0x0) 763 764 /* VTTBR_EL2 definitions */ 765 #define VTTBR_RESET_VAL ULL(0x0) 766 #define VTTBR_VMID_MASK ULL(0xff) 767 #define VTTBR_VMID_SHIFT U(48) 768 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 769 #define VTTBR_BADDR_SHIFT U(0) 770 771 /* HCR definitions */ 772 #define HCR_RESET_VAL ULL(0x0) 773 #define HCR_AMVOFFEN_SHIFT U(51) 774 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 775 #define HCR_TEA_BIT (ULL(1) << 47) 776 #define HCR_API_BIT (ULL(1) << 41) 777 #define HCR_APK_BIT (ULL(1) << 40) 778 #define HCR_E2H_BIT (ULL(1) << 34) 779 #define HCR_HCD_BIT (ULL(1) << 29) 780 #define HCR_TGE_BIT (ULL(1) << 27) 781 #define HCR_RW_SHIFT U(31) 782 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 783 #define HCR_TWE_BIT (ULL(1) << 14) 784 #define HCR_TWI_BIT (ULL(1) << 13) 785 #define HCR_AMO_BIT (ULL(1) << 5) 786 #define HCR_IMO_BIT (ULL(1) << 4) 787 #define HCR_FMO_BIT (ULL(1) << 3) 788 789 /* ISR definitions */ 790 #define ISR_A_SHIFT U(8) 791 #define ISR_I_SHIFT U(7) 792 #define ISR_F_SHIFT U(6) 793 794 /* CNTHCTL_EL2 definitions */ 795 #define CNTHCTL_RESET_VAL U(0x0) 796 #define EVNTEN_BIT (U(1) << 2) 797 #define EL1PCEN_BIT (U(1) << 1) 798 #define EL1PCTEN_BIT (U(1) << 0) 799 800 /* CNTKCTL_EL1 definitions */ 801 #define EL0PTEN_BIT (U(1) << 9) 802 #define EL0VTEN_BIT (U(1) << 8) 803 #define EL0PCTEN_BIT (U(1) << 0) 804 #define EL0VCTEN_BIT (U(1) << 1) 805 #define EVNTEN_BIT (U(1) << 2) 806 #define EVNTDIR_BIT (U(1) << 3) 807 #define EVNTI_SHIFT U(4) 808 #define EVNTI_MASK U(0xf) 809 810 /* CPTR_EL3 definitions */ 811 #define TCPAC_BIT (U(1) << 31) 812 #define TAM_SHIFT U(30) 813 #define TAM_BIT (U(1) << TAM_SHIFT) 814 #define TTA_BIT (U(1) << 20) 815 #define ESM_BIT (U(1) << 12) 816 #define TFP_BIT (U(1) << 10) 817 #define CPTR_EZ_BIT (U(1) << 8) 818 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 819 ~(CPTR_EZ_BIT | ESM_BIT)) 820 821 /* CPTR_EL2 definitions */ 822 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 823 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 824 #define CPTR_EL2_TAM_SHIFT U(30) 825 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 826 #define CPTR_EL2_SMEN_MASK ULL(0x3) 827 #define CPTR_EL2_SMEN_SHIFT U(24) 828 #define CPTR_EL2_TTA_BIT (U(1) << 20) 829 #define CPTR_EL2_ZEN_MASK ULL(0x3) 830 #define CPTR_EL2_ZEN_SHIFT U(16) 831 #define CPTR_EL2_TSM_BIT (U(1) << 12) 832 #define CPTR_EL2_TFP_BIT (ULL(1) << 10) 833 #define CPTR_EL2_TZ_BIT (ULL(1) << 8) 834 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 835 836 /* VTCR_EL2 definitions */ 837 #define VTCR_RESET_VAL U(0x0) 838 #define VTCR_EL2_MSA (U(1) << 31) 839 840 /* CPSR/SPSR definitions */ 841 #define DAIF_FIQ_BIT (U(1) << 0) 842 #define DAIF_IRQ_BIT (U(1) << 1) 843 #define DAIF_ABT_BIT (U(1) << 2) 844 #define DAIF_DBG_BIT (U(1) << 3) 845 #define SPSR_V_BIT (U(1) << 28) 846 #define SPSR_C_BIT (U(1) << 29) 847 #define SPSR_Z_BIT (U(1) << 30) 848 #define SPSR_N_BIT (U(1) << 31) 849 #define SPSR_DAIF_SHIFT U(6) 850 #define SPSR_DAIF_MASK U(0xf) 851 852 #define SPSR_AIF_SHIFT U(6) 853 #define SPSR_AIF_MASK U(0x7) 854 855 #define SPSR_E_SHIFT U(9) 856 #define SPSR_E_MASK U(0x1) 857 #define SPSR_E_LITTLE U(0x0) 858 #define SPSR_E_BIG U(0x1) 859 860 #define SPSR_T_SHIFT U(5) 861 #define SPSR_T_MASK U(0x1) 862 #define SPSR_T_ARM U(0x0) 863 #define SPSR_T_THUMB U(0x1) 864 865 #define SPSR_M_SHIFT U(4) 866 #define SPSR_M_MASK U(0x1) 867 #define SPSR_M_AARCH64 U(0x0) 868 #define SPSR_M_AARCH32 U(0x1) 869 #define SPSR_M_EL1H U(0x5) 870 #define SPSR_M_EL2H U(0x9) 871 872 #define SPSR_EL_SHIFT U(2) 873 #define SPSR_EL_WIDTH U(2) 874 875 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 876 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 877 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 878 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 879 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 880 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 881 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 882 #define SPSR_IL_BIT BIT_64(20) 883 #define SPSR_SS_BIT BIT_64(21) 884 #define SPSR_PAN_BIT BIT_64(22) 885 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 886 #define SPSR_DIT_BIT BIT(24) 887 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 888 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 889 #define SPSR_PPEND_BIT BIT(33) 890 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 891 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 892 #define SPSR_PACM_BIT_AARCH64 BIT_64(35) 893 894 /* 895 * SPSR_EL2 896 * M=0x9 (0b1001 EL2h) 897 * M[4]=0 898 * DAIF=0xF Exceptions masked on entry. 899 * BTYPE=0 BTI not yet supported. 900 * SSBS=0 Not yet supported. 901 * IL=0 Not an illegal exception return. 902 * SS=0 Not single stepping. 903 * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode. 904 * UAO=0 905 * DIT=0 906 * TCO=0 907 * NZCV=0 908 */ 909 #define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \ 910 SPSR_PAN_BIT) 911 912 #define DISABLE_ALL_EXCEPTIONS \ 913 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 914 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 915 916 /* 917 * RMR_EL3 definitions 918 */ 919 #define RMR_EL3_RR_BIT (U(1) << 1) 920 #define RMR_EL3_AA64_BIT (U(1) << 0) 921 922 /* 923 * HI-VECTOR address for AArch32 state 924 */ 925 #define HI_VECTOR_BASE U(0xFFFF0000) 926 927 /* 928 * TCR definitions 929 */ 930 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 931 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 932 #define TCR_EL1_IPS_SHIFT U(32) 933 #define TCR_EL2_PS_SHIFT U(16) 934 #define TCR_EL3_PS_SHIFT U(16) 935 936 #define TCR_TxSZ_MIN ULL(16) 937 #define TCR_TxSZ_MAX ULL(39) 938 #define TCR_TxSZ_MAX_TTST ULL(48) 939 940 #define TCR_T0SZ_SHIFT U(0) 941 #define TCR_T1SZ_SHIFT U(16) 942 943 /* (internal) physical address size bits in EL3/EL1 */ 944 #define TCR_PS_BITS_4GB ULL(0x0) 945 #define TCR_PS_BITS_64GB ULL(0x1) 946 #define TCR_PS_BITS_1TB ULL(0x2) 947 #define TCR_PS_BITS_4TB ULL(0x3) 948 #define TCR_PS_BITS_16TB ULL(0x4) 949 #define TCR_PS_BITS_256TB ULL(0x5) 950 951 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 952 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 953 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 954 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 955 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 956 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 957 958 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 959 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 960 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 961 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 962 963 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 964 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 965 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 966 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 967 968 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 969 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 970 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 971 972 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 973 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 974 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 975 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 976 977 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 978 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 979 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 980 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 981 982 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 983 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 984 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 985 986 #define TCR_TG0_SHIFT U(14) 987 #define TCR_TG0_MASK ULL(3) 988 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 989 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 990 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 991 992 #define TCR_TG1_SHIFT U(30) 993 #define TCR_TG1_MASK ULL(3) 994 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 995 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 996 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 997 998 #define TCR_EPD0_BIT (ULL(1) << 7) 999 #define TCR_EPD1_BIT (ULL(1) << 23) 1000 1001 #define MODE_SP_SHIFT U(0x0) 1002 #define MODE_SP_MASK U(0x1) 1003 #define MODE_SP_EL0 U(0x0) 1004 #define MODE_SP_ELX U(0x1) 1005 1006 #define MODE_RW_SHIFT U(0x4) 1007 #define MODE_RW_MASK U(0x1) 1008 #define MODE_RW_64 U(0x0) 1009 #define MODE_RW_32 U(0x1) 1010 1011 #define MODE_EL_SHIFT U(0x2) 1012 #define MODE_EL_MASK U(0x3) 1013 #define MODE_EL_WIDTH U(0x2) 1014 #define MODE_EL3 U(0x3) 1015 #define MODE_EL2 U(0x2) 1016 #define MODE_EL1 U(0x1) 1017 #define MODE_EL0 U(0x0) 1018 1019 #define MODE32_SHIFT U(0) 1020 #define MODE32_MASK U(0xf) 1021 #define MODE32_usr U(0x0) 1022 #define MODE32_fiq U(0x1) 1023 #define MODE32_irq U(0x2) 1024 #define MODE32_svc U(0x3) 1025 #define MODE32_mon U(0x6) 1026 #define MODE32_abt U(0x7) 1027 #define MODE32_hyp U(0xa) 1028 #define MODE32_und U(0xb) 1029 #define MODE32_sys U(0xf) 1030 1031 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 1032 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 1033 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 1034 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 1035 1036 #define SPSR_64(el, sp, daif) \ 1037 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 1038 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 1039 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 1040 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 1041 (~(SPSR_SSBS_BIT_AARCH64))) 1042 1043 #define SPSR_MODE32(mode, isa, endian, aif) \ 1044 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 1045 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 1046 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 1047 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 1048 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 1049 (~(SPSR_SSBS_BIT_AARCH32))) 1050 1051 /* 1052 * TTBR Definitions 1053 */ 1054 #define TTBR_CNP_BIT ULL(0x1) 1055 1056 /* 1057 * CTR_EL0 definitions 1058 */ 1059 #define CTR_CWG_SHIFT U(24) 1060 #define CTR_CWG_MASK U(0xf) 1061 #define CTR_ERG_SHIFT U(20) 1062 #define CTR_ERG_MASK U(0xf) 1063 #define CTR_DMINLINE_SHIFT U(16) 1064 #define CTR_DMINLINE_MASK U(0xf) 1065 #define CTR_L1IP_SHIFT U(14) 1066 #define CTR_L1IP_MASK U(0x3) 1067 #define CTR_IMINLINE_SHIFT U(0) 1068 #define CTR_IMINLINE_MASK U(0xf) 1069 1070 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1071 1072 /* Physical timer control register bit fields shifts and masks */ 1073 #define CNTP_CTL_ENABLE_SHIFT U(0) 1074 #define CNTP_CTL_IMASK_SHIFT U(1) 1075 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1076 1077 #define CNTP_CTL_ENABLE_MASK U(1) 1078 #define CNTP_CTL_IMASK_MASK U(1) 1079 #define CNTP_CTL_ISTATUS_MASK U(1) 1080 1081 /* Physical timer control macros */ 1082 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1083 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1084 1085 /* Exception Syndrome register bits and bobs */ 1086 #define ESR_EC_SHIFT U(26) 1087 #define ESR_EC_MASK U(0x3f) 1088 #define ESR_EC_LENGTH U(6) 1089 #define ESR_ISS_SHIFT U(0) 1090 #define ESR_ISS_LENGTH U(25) 1091 #define ESR_IL_BIT (U(1) << 25) 1092 #define EC_UNKNOWN U(0x0) 1093 #define EC_WFE_WFI U(0x1) 1094 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1095 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1096 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1097 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1098 #define EC_FP_SIMD U(0x7) 1099 #define EC_AARCH32_CP10_MRC U(0x8) 1100 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1101 #define EC_ILLEGAL U(0xe) 1102 #define EC_AARCH32_SVC U(0x11) 1103 #define EC_AARCH32_HVC U(0x12) 1104 #define EC_AARCH32_SMC U(0x13) 1105 #define EC_AARCH64_SVC U(0x15) 1106 #define EC_AARCH64_HVC U(0x16) 1107 #define EC_AARCH64_SMC U(0x17) 1108 #define EC_AARCH64_SYS U(0x18) 1109 #define EC_IMP_DEF_EL3 U(0x1f) 1110 #define EC_IABORT_LOWER_EL U(0x20) 1111 #define EC_IABORT_CUR_EL U(0x21) 1112 #define EC_PC_ALIGN U(0x22) 1113 #define EC_DABORT_LOWER_EL U(0x24) 1114 #define EC_DABORT_CUR_EL U(0x25) 1115 #define EC_SP_ALIGN U(0x26) 1116 #define EC_AARCH32_FP U(0x28) 1117 #define EC_AARCH64_FP U(0x2c) 1118 #define EC_SERROR U(0x2f) 1119 #define EC_BRK U(0x3c) 1120 1121 /* 1122 * External Abort bit in Instruction and Data Aborts synchronous exception 1123 * syndromes. 1124 */ 1125 #define ESR_ISS_EABORT_EA_BIT U(9) 1126 1127 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1128 1129 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1130 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1131 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1132 1133 /******************************************************************************* 1134 * Definitions of register offsets, fields and macros for CPU system 1135 * instructions. 1136 ******************************************************************************/ 1137 1138 #define TLBI_ADDR_SHIFT U(12) 1139 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1140 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1141 1142 /******************************************************************************* 1143 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1144 * system level implementation of the Generic Timer. 1145 ******************************************************************************/ 1146 #define CNTCTLBASE_CNTFRQ U(0x0) 1147 #define CNTNSAR U(0x4) 1148 #define CNTNSAR_NS_SHIFT(x) (x) 1149 1150 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1151 #define CNTACR_RPCT_SHIFT U(0x0) 1152 #define CNTACR_RVCT_SHIFT U(0x1) 1153 #define CNTACR_RFRQ_SHIFT U(0x2) 1154 #define CNTACR_RVOFF_SHIFT U(0x3) 1155 #define CNTACR_RWVT_SHIFT U(0x4) 1156 #define CNTACR_RWPT_SHIFT U(0x5) 1157 1158 /******************************************************************************* 1159 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1160 * system level implementation of the Generic Timer. 1161 ******************************************************************************/ 1162 /* Physical Count register. */ 1163 #define CNTPCT_LO U(0x0) 1164 /* Counter Frequency register. */ 1165 #define CNTBASEN_CNTFRQ U(0x10) 1166 /* Physical Timer CompareValue register. */ 1167 #define CNTP_CVAL_LO U(0x20) 1168 /* Physical Timer Control register. */ 1169 #define CNTP_CTL U(0x2c) 1170 1171 /* PMCR_EL0 definitions */ 1172 #define PMCR_EL0_RESET_VAL U(0x0) 1173 #define PMCR_EL0_N_SHIFT U(11) 1174 #define PMCR_EL0_N_MASK U(0x1f) 1175 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1176 #define PMCR_EL0_LP_BIT (U(1) << 7) 1177 #define PMCR_EL0_LC_BIT (U(1) << 6) 1178 #define PMCR_EL0_DP_BIT (U(1) << 5) 1179 #define PMCR_EL0_X_BIT (U(1) << 4) 1180 #define PMCR_EL0_D_BIT (U(1) << 3) 1181 #define PMCR_EL0_C_BIT (U(1) << 2) 1182 #define PMCR_EL0_P_BIT (U(1) << 1) 1183 #define PMCR_EL0_E_BIT (U(1) << 0) 1184 1185 /******************************************************************************* 1186 * Definitions for system register interface to SVE 1187 ******************************************************************************/ 1188 #define ZCR_EL3 S3_6_C1_C2_0 1189 #define ZCR_EL2 S3_4_C1_C2_0 1190 1191 /* ZCR_EL3 definitions */ 1192 #define ZCR_EL3_LEN_MASK U(0xf) 1193 1194 /* ZCR_EL2 definitions */ 1195 #define ZCR_EL2_LEN_MASK U(0xf) 1196 1197 /******************************************************************************* 1198 * Definitions for system register interface to SME as needed in EL3 1199 ******************************************************************************/ 1200 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1201 #define SMCR_EL3 S3_6_C1_C2_6 1202 #define SVCR S3_3_C4_C2_2 1203 1204 /* ID_AA64SMFR0_EL1 definitions */ 1205 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1206 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1207 #define SME_FA64_IMPLEMENTED U(0x1) 1208 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1209 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1210 #define SME_INST_IMPLEMENTED ULL(0x0) 1211 #define SME2_INST_IMPLEMENTED ULL(0x1) 1212 1213 /* SMCR_ELx definitions */ 1214 #define SMCR_ELX_LEN_SHIFT U(0) 1215 #define SMCR_ELX_LEN_MAX U(0x1ff) 1216 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1217 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1218 1219 /******************************************************************************* 1220 * Definitions of MAIR encodings for device and normal memory 1221 ******************************************************************************/ 1222 /* 1223 * MAIR encodings for device memory attributes. 1224 */ 1225 #define MAIR_DEV_nGnRnE ULL(0x0) 1226 #define MAIR_DEV_nGnRE ULL(0x4) 1227 #define MAIR_DEV_nGRE ULL(0x8) 1228 #define MAIR_DEV_GRE ULL(0xc) 1229 1230 /* 1231 * MAIR encodings for normal memory attributes. 1232 * 1233 * Cache Policy 1234 * WT: Write Through 1235 * WB: Write Back 1236 * NC: Non-Cacheable 1237 * 1238 * Transient Hint 1239 * NTR: Non-Transient 1240 * TR: Transient 1241 * 1242 * Allocation Policy 1243 * RA: Read Allocate 1244 * WA: Write Allocate 1245 * RWA: Read and Write Allocate 1246 * NA: No Allocation 1247 */ 1248 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1249 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1250 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1251 #define MAIR_NORM_NC ULL(0x4) 1252 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1253 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1254 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1255 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1256 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1257 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1258 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1259 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1260 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1261 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1262 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1263 1264 #define MAIR_NORM_OUTER_SHIFT U(4) 1265 1266 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1267 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1268 1269 /* PAR_EL1 fields */ 1270 #define PAR_F_SHIFT U(0) 1271 #define PAR_F_MASK ULL(0x1) 1272 1273 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1274 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1275 1276 /******************************************************************************* 1277 * Definitions for system register interface to SPE 1278 ******************************************************************************/ 1279 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1280 1281 /******************************************************************************* 1282 * Definitions for system register interface, shifts and masks for MPAM 1283 ******************************************************************************/ 1284 #define MPAMIDR_EL1 S3_0_C10_C4_4 1285 #define MPAM2_EL2 S3_4_C10_C5_0 1286 #define MPAMHCR_EL2 S3_4_C10_C4_0 1287 #define MPAM3_EL3 S3_6_C10_C5_0 1288 1289 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1290 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1291 /******************************************************************************* 1292 * Definitions for system register interface to AMU for FEAT_AMUv1 1293 ******************************************************************************/ 1294 #define AMCR_EL0 S3_3_C13_C2_0 1295 #define AMCFGR_EL0 S3_3_C13_C2_1 1296 #define AMCGCR_EL0 S3_3_C13_C2_2 1297 #define AMUSERENR_EL0 S3_3_C13_C2_3 1298 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1299 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1300 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1301 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1302 1303 /* Activity Monitor Group 0 Event Counter Registers */ 1304 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1305 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1306 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1307 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1308 1309 /* Activity Monitor Group 0 Event Type Registers */ 1310 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1311 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1312 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1313 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1314 1315 /* Activity Monitor Group 1 Event Counter Registers */ 1316 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1317 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1318 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1319 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1320 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1321 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1322 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1323 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1324 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1325 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1326 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1327 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1328 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1329 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1330 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1331 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1332 1333 /* Activity Monitor Group 1 Event Type Registers */ 1334 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1335 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1336 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1337 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1338 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1339 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1340 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1341 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1342 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1343 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1344 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1345 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1346 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1347 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1348 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1349 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1350 1351 /* AMCNTENSET0_EL0 definitions */ 1352 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1353 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1354 1355 /* AMCNTENSET1_EL0 definitions */ 1356 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1357 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1358 1359 /* AMCNTENCLR0_EL0 definitions */ 1360 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1361 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1362 1363 /* AMCNTENCLR1_EL0 definitions */ 1364 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1365 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1366 1367 /* AMCFGR_EL0 definitions */ 1368 #define AMCFGR_EL0_NCG_SHIFT U(28) 1369 #define AMCFGR_EL0_NCG_MASK U(0xf) 1370 #define AMCFGR_EL0_N_SHIFT U(0) 1371 #define AMCFGR_EL0_N_MASK U(0xff) 1372 1373 /* AMCGCR_EL0 definitions */ 1374 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1375 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1376 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1377 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1378 1379 /* MPAM register definitions */ 1380 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1381 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1382 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1383 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1384 1385 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1386 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1387 1388 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56) 1389 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1390 1391 /* MPAM_PE_BW_CTRL register definitions */ 1392 #define MPAMBW2_EL2 S3_4_C10_C5_4 1393 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1394 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62) 1395 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61) 1396 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52) 1397 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51) 1398 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50) 1399 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49) 1400 1401 #define MPAMBW3_EL3 S3_6_C10_C5_4 1402 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1403 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62) 1404 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61) 1405 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49) 1406 1407 /******************************************************************************* 1408 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1409 ******************************************************************************/ 1410 1411 /* Definition for register defining which virtual offsets are implemented. */ 1412 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1413 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1414 #define AMCG1IDR_CTR_SHIFT U(0) 1415 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1416 #define AMCG1IDR_VOFF_SHIFT U(16) 1417 1418 /* New bit added to AMCR_EL0 */ 1419 #define AMCR_CG1RZ_SHIFT U(17) 1420 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1421 1422 /* 1423 * Definitions for virtual offset registers for architected activity monitor 1424 * event counters. 1425 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1426 */ 1427 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1428 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1429 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1430 1431 /* 1432 * Definitions for virtual offset registers for auxiliary activity monitor event 1433 * counters. 1434 */ 1435 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1436 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1437 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1438 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1439 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1440 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1441 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1442 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1443 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1444 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1445 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1446 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1447 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1448 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1449 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1450 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1451 1452 /******************************************************************************* 1453 * Realm management extension register definitions 1454 ******************************************************************************/ 1455 #define GPCCR_EL3 S3_6_C2_C1_6 1456 #define GPTBR_EL3 S3_6_C2_C1_4 1457 1458 #define SCXTNUM_EL2 S3_4_C13_C0_7 1459 #define SCXTNUM_EL1 S3_0_C13_C0_7 1460 #define SCXTNUM_EL0 S3_3_C13_C0_7 1461 1462 /******************************************************************************* 1463 * RAS system registers 1464 ******************************************************************************/ 1465 #define DISR_EL1 S3_0_C12_C1_1 1466 #define DISR_A_BIT U(31) 1467 1468 #define ERRIDR_EL1 S3_0_C5_C3_0 1469 #define ERRIDR_MASK U(0xffff) 1470 1471 #define ERRSELR_EL1 S3_0_C5_C3_1 1472 1473 /* System register access to Standard Error Record registers */ 1474 #define ERXFR_EL1 S3_0_C5_C4_0 1475 #define ERXCTLR_EL1 S3_0_C5_C4_1 1476 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1477 #define ERXADDR_EL1 S3_0_C5_C4_3 1478 #define ERXPFGF_EL1 S3_0_C5_C4_4 1479 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1480 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1481 #define ERXMISC0_EL1 S3_0_C5_C5_0 1482 #define ERXMISC1_EL1 S3_0_C5_C5_1 1483 1484 #define ERXCTLR_ED_SHIFT U(0) 1485 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1486 #define ERXCTLR_UE_BIT (U(1) << 4) 1487 1488 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1489 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1490 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1491 1492 /******************************************************************************* 1493 * Armv8.3 Pointer Authentication Registers 1494 ******************************************************************************/ 1495 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1496 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1497 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1498 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1499 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1500 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1501 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1502 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1503 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1504 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1505 1506 /******************************************************************************* 1507 * Armv8.4 Data Independent Timing Registers 1508 ******************************************************************************/ 1509 #define DIT S3_3_C4_C2_5 1510 #define DIT_BIT BIT(24) 1511 1512 /******************************************************************************* 1513 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1514 ******************************************************************************/ 1515 #define SSBS S3_3_C4_C2_6 1516 1517 /******************************************************************************* 1518 * Armv8.5 - Memory Tagging Extension Registers 1519 ******************************************************************************/ 1520 #define TFSRE0_EL1 S3_0_C5_C6_1 1521 #define TFSR_EL1 S3_0_C5_C6_0 1522 #define RGSR_EL1 S3_0_C1_C0_5 1523 #define GCR_EL1 S3_0_C1_C0_6 1524 1525 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1526 1527 /******************************************************************************* 1528 * Armv8.5 - Random Number Generator Registers 1529 ******************************************************************************/ 1530 #define RNDR S3_3_C2_C4_0 1531 #define RNDRRS S3_3_C2_C4_1 1532 1533 /******************************************************************************* 1534 * FEAT_HCX - Extended Hypervisor Configuration Register 1535 ******************************************************************************/ 1536 #define HCRX_EL2 S3_4_C1_C2_2 1537 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1538 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1539 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1540 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1541 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1542 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1543 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1544 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1545 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1546 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1547 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1548 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1549 #define HCRX_EL2_INIT_VAL ULL(0x0) 1550 1551 /******************************************************************************* 1552 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1553 ******************************************************************************/ 1554 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1555 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1556 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1557 1558 /******************************************************************************* 1559 * FEAT_TCR2 - Extended Translation Control Registers 1560 ******************************************************************************/ 1561 #define TCR2_EL1 S3_0_C2_C0_3 1562 #define TCR2_EL2 S3_4_C2_C0_3 1563 1564 /******************************************************************************* 1565 * Permission indirection and overlay Registers 1566 ******************************************************************************/ 1567 1568 #define PIRE0_EL1 S3_0_C10_C2_2 1569 #define PIRE0_EL2 S3_4_C10_C2_2 1570 #define PIR_EL1 S3_0_C10_C2_3 1571 #define PIR_EL2 S3_4_C10_C2_3 1572 #define POR_EL1 S3_0_C10_C2_4 1573 #define POR_EL2 S3_4_C10_C2_4 1574 #define S2PIR_EL2 S3_4_C10_C2_5 1575 #define S2POR_EL1 S3_0_C10_C2_5 1576 1577 /******************************************************************************* 1578 * FEAT_GCS - Guarded Control Stack Registers 1579 ******************************************************************************/ 1580 #define GCSCR_EL2 S3_4_C2_C5_0 1581 #define GCSPR_EL2 S3_4_C2_C5_1 1582 #define GCSCR_EL1 S3_0_C2_C5_0 1583 #define GCSCRE0_EL1 S3_0_C2_C5_2 1584 #define GCSPR_EL1 S3_0_C2_C5_1 1585 #define GCSPR_EL0 S3_3_C2_C5_1 1586 1587 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1588 1589 /******************************************************************************* 1590 * FEAT_TRF - Trace Filter Control Registers 1591 ******************************************************************************/ 1592 #define TRFCR_EL2 S3_4_C1_C2_1 1593 #define TRFCR_EL1 S3_0_C1_C2_1 1594 1595 /******************************************************************************* 1596 * FEAT_THE - Translation Hardening Extension Registers 1597 ******************************************************************************/ 1598 #define RCWMASK_EL1 S3_0_C13_C0_6 1599 #define RCWSMASK_EL1 S3_0_C13_C0_3 1600 1601 /******************************************************************************* 1602 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1603 ******************************************************************************/ 1604 #define SCTLR2_EL3 S3_6_C1_C0_3 1605 #define SCTLR2_EL2 S3_4_C1_C0_3 1606 #define SCTLR2_EL1 S3_0_C1_C0_3 1607 1608 /******************************************************************************* 1609 * FEAT_BRBE - Branch Record Buffer Extension Registers 1610 ******************************************************************************/ 1611 #define BRBCR_EL2 S2_4_C9_C0_0 1612 1613 /******************************************************************************* 1614 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1615 ******************************************************************************/ 1616 #define ACCDATA_EL1 S3_0_C13_C0_5 1617 1618 /******************************************************************************* 1619 * Definitions for DynamicIQ Shared Unit registers 1620 ******************************************************************************/ 1621 #define CLUSTERPWRDN_EL1 S3_0_C15_C3_6 1622 1623 /******************************************************************************* 1624 * FEAT_FPMR - Floating point Mode Register 1625 ******************************************************************************/ 1626 #define FPMR S3_3_C4_C4_2 1627 1628 /* CLUSTERPWRDN_EL1 register definitions */ 1629 #define DSU_CLUSTER_PWR_OFF 0 1630 #define DSU_CLUSTER_PWR_ON 1 1631 #define DSU_CLUSTER_PWR_MASK U(1) 1632 #define DSU_CLUSTER_MEM_RET BIT(1) 1633 1634 /******************************************************************************* 1635 * Definitions for CPU Power/Performance Management registers 1636 ******************************************************************************/ 1637 1638 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1639 #define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) 1640 1641 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1642 #define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) 1643 1644 /* alternative system register encoding for the "sb" speculation barrier */ 1645 #define SYSREG_SB S0_3_C3_C0_7 1646 1647 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1648 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1649 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1650 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1651 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1652 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1653 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1654 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1655 1656 #define CLUSTERPMCR_E_BIT BIT(0) 1657 #define CLUSTERPMCR_N_SHIFT U(11) 1658 #define CLUSTERPMCR_N_MASK U(0x1f) 1659 1660 /******************************************************************************* 1661 * FEAT_MEC - Memory Encryption Contexts 1662 ******************************************************************************/ 1663 #define MECIDR_EL2 S3_4_C10_C8_7 1664 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) 1665 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) 1666 1667 /****************************************************************************** 1668 * FEAT_FGWTE3 - Fine Grained Write Trap 1669 ******************************************************************************/ 1670 #define FGWTE3_EL3 S3_6_C1_C1_5 1671 1672 /* FGWTE3_EL3 Defintions */ 1673 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21) 1674 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20) 1675 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19) 1676 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18) 1677 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17) 1678 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16) 1679 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15) 1680 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14) 1681 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12) 1682 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10) 1683 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9) 1684 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8) 1685 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7) 1686 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6) 1687 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5) 1688 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4) 1689 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3) 1690 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2) 1691 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1) 1692 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0) 1693 1694 #define FGWTE3_EL3_EARLY_INIT_VAL ( \ 1695 FGWTE3_EL3_VBAR_EL3_BIT | \ 1696 FGWTE3_EL3_TTBR0_EL3_BIT | \ 1697 FGWTE3_EL3_SPMROOTCR_EL3_BIT | \ 1698 FGWTE3_EL3_SCTLR2_EL3_BIT | \ 1699 FGWTE3_EL3_PIR_EL3_BIT | \ 1700 FGWTE3_EL3_MECID_RL_A_EL3_BIT | \ 1701 FGWTE3_EL3_MAIR2_EL3_BIT | \ 1702 FGWTE3_EL3_MAIR_EL3_BIT | \ 1703 FGWTE3_EL3_GPTBR_EL3_BIT | \ 1704 FGWTE3_EL3_GPCCR_EL3_BIT | \ 1705 FGWTE3_EL3_GCSPR_EL3_BIT | \ 1706 FGWTE3_EL3_GCSCR_EL3_BIT | \ 1707 FGWTE3_EL3_AMAIR2_EL3_BIT | \ 1708 FGWTE3_EL3_AMAIR_EL3_BIT | \ 1709 FGWTE3_EL3_AFSR1_EL3_BIT | \ 1710 FGWTE3_EL3_AFSR0_EL3_BIT) 1711 1712 #if HW_ASSISTED_COHERENCY 1713 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT | 1714 #else 1715 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT 1716 #endif 1717 1718 #if !(CRASH_REPORTING) 1719 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT | 1720 #else 1721 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT 1722 #endif 1723 1724 #define FGWTE3_EL3_LATE_INIT_VAL ( \ 1725 FGWTE3_EL3_EARLY_INIT_VAL | \ 1726 FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT \ 1727 FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT \ 1728 FGWTE3_EL3_TCR_EL3_BIT | \ 1729 FGWTE3_EL3_ACTLR_EL3_BIT) 1730 1731 #endif /* ARCH_H */ 1732