1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27ifeq (${ENABLE_RME},1) 28FVP_TRUSTED_SRAM_SIZE := 384 29else 30FVP_TRUSTED_SRAM_SIZE := 256 31endif 32 33# Macro to enable helpers for running SPM tests. Disabled by default. 34PLAT_TEST_SPM := 0 35 36 37# Enable passing the DT to BL33 in x0 by default. 38USE_KERNEL_DT_CONVENTION := 1 39 40# By default dont build CPUs with no FVP model. 41BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 42 43ENABLE_FEAT_AMU := 2 44ENABLE_FEAT_AMUv1p1 := 2 45ENABLE_FEAT_HCX := 2 46ENABLE_FEAT_RNG := 2 47ENABLE_FEAT_TWED := 2 48ENABLE_FEAT_GCS := 2 49 50ifeq (${ARCH}, aarch64) 51 52ifeq (${SPM_MM}, 0) 53ifeq (${CTX_INCLUDE_FPREGS}, 0) 54 ENABLE_SME_FOR_NS := 2 55 ENABLE_SME2_FOR_NS := 2 56else 57 ENABLE_SVE_FOR_NS := 0 58 ENABLE_SME_FOR_NS := 0 59 ENABLE_SME2_FOR_NS := 0 60endif 61endif 62 63 ENABLE_BRBE_FOR_NS := 2 64 ENABLE_TRBE_FOR_NS := 2 65 ENABLE_FEAT_D128 := 2 66 ENABLE_FEAT_FPMR := 2 67 ENABLE_FEAT_MOPS := 2 68 ENABLE_FEAT_FGWTE3 := 2 69 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 70endif 71 72ENABLE_SYS_REG_TRACE_FOR_NS := 2 73ENABLE_FEAT_CSV2_2 := 2 74ENABLE_FEAT_CSV2_3 := 2 75ENABLE_FEAT_DEBUGV8P9 := 2 76ENABLE_FEAT_DIT := 2 77ENABLE_FEAT_PAN := 2 78ENABLE_FEAT_VHE := 2 79CTX_INCLUDE_NEVE_REGS := 2 80ENABLE_FEAT_SEL2 := 2 81ENABLE_TRF_FOR_NS := 2 82ENABLE_FEAT_ECV := 2 83ENABLE_FEAT_FGT := 2 84ENABLE_FEAT_FGT2 := 2 85ENABLE_FEAT_THE := 2 86ENABLE_FEAT_TCR2 := 2 87ENABLE_FEAT_S2PIE := 2 88ENABLE_FEAT_S1PIE := 2 89ENABLE_FEAT_S2POE := 2 90ENABLE_FEAT_S1POE := 2 91ENABLE_FEAT_SCTLR2 := 2 92ENABLE_FEAT_MTE2 := 2 93ENABLE_FEAT_LS64_ACCDATA := 2 94 95ifeq (${ENABLE_RME},1) 96 ENABLE_FEAT_MEC := 2 97 RMMD_ENABLE_IDE_KEY_PROG := 1 98endif 99 100# The FVP platform depends on this macro to build with correct GIC driver. 101$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 102 103# Pass FVP_CLUSTER_COUNT to the build system. 104$(eval $(call add_define,FVP_CLUSTER_COUNT)) 105 106# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 107$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 108 109# Pass FVP_MAX_PE_PER_CPU to the build system. 110$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 111 112# Pass FVP_GICR_REGION_PROTECTION to the build system. 113$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 114 115# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 116$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 117 118# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 119# choose the CCI driver , else the CCN driver 120ifeq ($(FVP_CLUSTER_COUNT), 0) 121$(error "Incorrect cluster count specified for FVP port") 122else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 123FVP_INTERCONNECT_DRIVER := FVP_CCI 124else 125FVP_INTERCONNECT_DRIVER := FVP_CCN 126endif 127 128$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 129 130# Choose the GIC sources depending upon the how the FVP will be invoked 131ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 132USE_GIC_DRIVER := 3 133 134# The GIC model (GIC-600 or GIC-500) will be detected at runtime 135GICV3_SUPPORT_GIC600 := 1 136GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 137 138FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 139ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 140BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 141endif 142 143ifeq (${HW_ASSISTED_COHERENCY}, 0) 144FVP_DT_PREFIX := fvp-base-gicv3-psci 145else 146FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 147endif 148else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 149USE_GIC_DRIVER := 5 150ENABLE_FEAT_GCIE := 1 151BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 152FVP_DT_PREFIX := fvp-base-gicv5-psci 153ifneq ($(SPD),none) 154 $(error Error: GICv5 is not compatible with SPDs) 155endif 156ifeq ($(ENABLE_RME),1) 157 $(error Error: GICv5 is not compatible with RME) 158endif 159else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 160USE_GIC_DRIVER := 2 161 162# No GICv4 extension 163GIC_ENABLE_V4_EXTN := 0 164$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 165 166FVP_DT_PREFIX := fvp-base-gicv2-psci 167else 168$(error "Incorrect GIC driver chosen on FVP port") 169endif 170 171ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 172FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 173else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 174FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 175 plat/arm/common/arm_ccn.c 176else 177$(error "Incorrect CCN driver chosen on FVP port") 178endif 179 180FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 181 plat/arm/board/fvp/fvp_security.c \ 182 plat/arm/common/arm_tzc400.c 183 184 185PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 186 -Iinclude/lib/psa 187 188 189PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 190 191FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 192 193ifeq (${ARCH}, aarch64) 194 195# select a different set of CPU files, depending on whether we compile for 196# hardware assisted coherency cores or not 197ifeq (${HW_ASSISTED_COHERENCY}, 0) 198# Cores used without DSU 199 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 200 lib/cpus/aarch64/cortex_a53.S \ 201 lib/cpus/aarch64/cortex_a57.S \ 202 lib/cpus/aarch64/cortex_a72.S \ 203 lib/cpus/aarch64/cortex_a73.S 204else 205# Cores used with DSU only 206 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 207 # AArch64-only cores 208 # TODO: add all cores to the appropriate lists 209 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 210 lib/cpus/aarch64/cortex_a65ae.S \ 211 lib/cpus/aarch64/cortex_a76.S \ 212 lib/cpus/aarch64/cortex_a76ae.S \ 213 lib/cpus/aarch64/cortex_a77.S \ 214 lib/cpus/aarch64/cortex_a78.S \ 215 lib/cpus/aarch64/cortex_a78_ae.S \ 216 lib/cpus/aarch64/cortex_a78c.S \ 217 lib/cpus/aarch64/cortex_a710.S \ 218 lib/cpus/aarch64/cortex_a715.S \ 219 lib/cpus/aarch64/cortex_a720.S \ 220 lib/cpus/aarch64/cortex_a720_ae.S \ 221 lib/cpus/aarch64/neoverse_n1.S \ 222 lib/cpus/aarch64/neoverse_n2.S \ 223 lib/cpus/aarch64/neoverse_v1.S \ 224 lib/cpus/aarch64/neoverse_e1.S \ 225 lib/cpus/aarch64/cortex_x2.S \ 226 lib/cpus/aarch64/cortex_x4.S 227 endif 228 # AArch64/AArch32 cores 229 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 230 lib/cpus/aarch64/cortex_a75.S 231endif 232 233#Include all CPUs to build to support all-errata build. 234ifeq (${ENABLE_ERRATA_ALL},1) 235 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 236 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 237 lib/cpus/aarch64/cortex_a510.S \ 238 lib/cpus/aarch64/cortex_a520.S \ 239 lib/cpus/aarch64/cortex_a725.S \ 240 lib/cpus/aarch64/cortex_x1.S \ 241 lib/cpus/aarch64/cortex_x3.S \ 242 lib/cpus/aarch64/cortex_x925.S \ 243 lib/cpus/aarch64/neoverse_n3.S \ 244 lib/cpus/aarch64/neoverse_v2.S \ 245 lib/cpus/aarch64/neoverse_v3.S 246endif 247 248#Build AArch64-only CPUs with no FVP model yet. 249ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 250 ERRATA_SME_POWER_DOWN := 1 251 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 252 lib/cpus/aarch64/c1_nano.S \ 253 lib/cpus/aarch64/c1_ultra.S \ 254 lib/cpus/aarch64/c1_premium.S \ 255 lib/cpus/aarch64/canyon.S 256endif 257 258else 259FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 260 lib/cpus/aarch32/cortex_a57.S \ 261 lib/cpus/aarch32/cortex_a53.S 262endif 263 264BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 265 drivers/arm/sp805/sp805.c \ 266 drivers/delay_timer/delay_timer.c \ 267 drivers/io/io_semihosting.c \ 268 lib/semihosting/semihosting.c \ 269 lib/semihosting/${ARCH}/semihosting_call.S \ 270 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 271 plat/arm/board/fvp/fvp_bl1_setup.c \ 272 plat/arm/board/fvp/fvp_cpu_pwr.c \ 273 plat/arm/board/fvp/fvp_err.c \ 274 plat/arm/board/fvp/fvp_io_storage.c \ 275 plat/arm/board/fvp/fvp_topology.c \ 276 ${FVP_CPU_LIBS} \ 277 ${FVP_INTERCONNECT_SOURCES} 278 279ifeq (${USE_SP804_TIMER},1) 280BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 281else 282BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 283endif 284 285 286BL2_SOURCES += drivers/arm/sp805/sp805.c \ 287 drivers/io/io_semihosting.c \ 288 lib/utils/mem_region.c \ 289 lib/semihosting/semihosting.c \ 290 lib/semihosting/${ARCH}/semihosting_call.S \ 291 plat/arm/board/fvp/fvp_bl2_setup.c \ 292 plat/arm/board/fvp/fvp_err.c \ 293 plat/arm/board/fvp/fvp_io_storage.c \ 294 plat/arm/common/arm_nor_psci_mem_protect.c \ 295 ${FVP_SECURITY_SOURCES} 296 297 298ifeq (${COT_DESC_IN_DTB},1) 299BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 300endif 301 302ifeq (${ENABLE_RME},1) 303BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 304 plat/arm/board/fvp/fvp_cpu_pwr.c 305 306BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 307 plat/arm/board/fvp/fvp_realm_attest_key.c \ 308 plat/arm/board/fvp/fvp_el3_token_sign.c \ 309 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 310 plat/arm/common/plat_rmm_mem_carveout.c 311endif 312 313ifneq (${ENABLE_FEAT_RNG_TRAP},0) 314BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 315endif 316 317ifeq (${RESET_TO_BL2},1) 318BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 319 plat/arm/board/fvp/fvp_cpu_pwr.c \ 320 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 321 ${FVP_CPU_LIBS} \ 322 ${FVP_INTERCONNECT_SOURCES} 323endif 324 325ifeq (${USE_SP804_TIMER},1) 326BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 327endif 328 329BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 330 ${FVP_SECURITY_SOURCES} 331 332ifeq (${USE_SP804_TIMER},1) 333BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 334endif 335 336BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 337 drivers/arm/smmu/smmu_v3.c \ 338 drivers/delay_timer/delay_timer.c \ 339 drivers/cfi/v2m/v2m_flash.c \ 340 lib/utils/mem_region.c \ 341 plat/arm/board/fvp/fvp_bl31_setup.c \ 342 plat/arm/board/fvp/fvp_console.c \ 343 plat/arm/board/fvp/fvp_pm.c \ 344 plat/arm/board/fvp/fvp_topology.c \ 345 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 346 plat/arm/board/fvp/fvp_cpu_pwr.c \ 347 plat/arm/common/arm_nor_psci_mem_protect.c \ 348 ${FVP_CPU_LIBS} \ 349 ${FVP_INTERCONNECT_SOURCES} \ 350 ${FVP_SECURITY_SOURCES} 351 352# Support for fconf in BL31 353# Added separately from the above list for better readability 354ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 355BL31_SOURCES += lib/fconf/fconf.c \ 356 lib/fconf/fconf_dyn_cfg_getter.c \ 357 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 358 359BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 360 361ifeq (${SEC_INT_DESC_IN_FCONF},1) 362BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 363endif 364 365endif 366 367ifeq (${USE_SP804_TIMER},1) 368BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 369else 370BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 371endif 372 373# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 374FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 375 376FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 377$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 378HW_CONFIG := ${FVP_HW_CONFIG} 379 380HW_CONFIG_BASE ?= 0x82000000 381 382# Set default initrd base 128MiB offset of the default kernel address in FVP 383INITRD_BASE ?= 0x90000000 384 385# Kernel base address supports Linux kernels before v5.7 386# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 387ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 388 PRELOADED_BL33_BASE ?= 0x80080000 389 ifeq (${RESET_TO_BL31},1) 390 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 391 endif 392endif 393 394ifeq (${TRANSFER_LIST}, 0) 395FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 396 ${PLAT}_fw_config.dts \ 397 ${PLAT}_tb_fw_config.dts \ 398 ${PLAT}_soc_fw_config.dts \ 399 ${PLAT}_nt_fw_config.dts \ 400 ) 401 402FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 403FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 404FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 405FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 406 407ifeq (${SPD},tspd) 408FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 409FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 410 411# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 412$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 413endif 414 415# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 416$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 417# Add the NT_FW_CONFIG to FIP and specify the same to certtool 418$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 419endif 420 421ifeq (${SPD},spmd) 422 423ifeq ($(ARM_SPMC_MANIFEST_DTS),) 424ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 425endif 426 427FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 428FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 429 430# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 431$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 432endif 433 434# Add the HW_CONFIG to FIP and specify the same to certtool 435$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 436 437ifeq (${TRANSFER_LIST}, 1) 438 439ifeq ($(RESET_TO_BL31), 1) 440FW_HANDOFF_SIZE := 20000 441 442TRANSFER_LIST_DTB_OFFSET := 0x20 443$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 444endif 445endif 446 447ifeq (${HOB_LIST}, 1) 448include lib/hob/hob.mk 449endif 450 451# Enable dynamic mitigation support by default 452DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 453 454ifneq (${ENABLE_FEAT_AMU},0) 455BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 456 lib/cpus/aarch64/cpuamu_helpers.S 457 458ifeq (${HW_ASSISTED_COHERENCY}, 1) 459BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 460 lib/cpus/aarch64/neoverse_n1_pubsub.c 461endif 462endif 463 464ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 465 ifeq (${ENABLE_FEAT_RAS},1) 466 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 467 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 468 else 469 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 470 endif 471 else 472 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 473 endif 474endif 475 476ifneq (${ENABLE_STACK_PROTECTOR},0) 477PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 478endif 479 480# Enable the dynamic translation tables library. 481ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 482 ifeq (${ARCH},aarch32) 483 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 484 else # AArch64 485 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 486 endif 487endif 488 489ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 490 ifeq (${ARCH},aarch32) 491 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 492 else # AArch64 493 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 494 ifeq (${SPD},tspd) 495 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 496 endif 497 endif 498endif 499 500ifeq (${USE_DEBUGFS},1) 501 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 502endif 503 504# Add support for platform supplied linker script for BL31 build 505$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 506 507ifneq (${RESET_TO_BL2}, 0) 508 override BL1_SOURCES = 509endif 510 511include plat/arm/board/common/board_common.mk 512include plat/arm/common/arm_common.mk 513 514ifeq (${MEASURED_BOOT},1) 515BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 516 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 517 lib/psa/measured_boot.c 518 519BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 520 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 521 lib/psa/measured_boot.c 522endif 523 524ifeq (${DRTM_SUPPORT}, 1) 525BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 526 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 527 plat/arm/board/fvp/fvp_drtm_err.c \ 528 plat/arm/board/fvp/fvp_drtm_measurement.c \ 529 plat/arm/board/fvp/fvp_drtm_stub.c \ 530 plat/arm/common/arm_dyn_cfg.c \ 531 plat/arm/board/fvp/fvp_err.c 532endif 533 534ifeq (${TRUSTED_BOARD_BOOT}, 1) 535BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 536BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 537 538# FVP being a development platform, enable capability to disable Authentication 539# dynamically if TRUSTED_BOARD_BOOT is set. 540DYN_DISABLE_AUTH := 1 541endif 542 543ifeq (${SPMC_AT_EL3}, 1) 544PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 545endif 546 547PSCI_OS_INIT_MODE := 1 548 549ifeq (${SPD},spmd) 550BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 551endif 552 553# Test specific macros, keep them at bottom of this file 554$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 555ifeq (${PLATFORM_TEST_EA_FFH}, 1) 556 ifeq (${FFH_SUPPORT}, 0) 557 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 558 endif 559 560endif 561 562$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 563ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 564 ifeq (${ENABLE_FEAT_RAS}, 0) 565 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 566 endif 567 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 568 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 569 endif 570endif 571 572$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 573ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 574 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 575 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 576 endif 577 ifeq (${ENABLE_SPMD_LP}, 0) 578 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 579 endif 580 ifeq (${ENABLE_FEAT_RAS}, 0) 581 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 582 endif 583 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 584 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 585 endif 586endif 587 588ifeq (${ERRATA_ABI_SUPPORT}, 1) 589include plat/arm/board/fvp/fvp_cpu_errata.mk 590endif 591 592# Build macro necessary for running SPM tests on FVP platform 593$(eval $(call add_define,PLAT_TEST_SPM)) 594 595ifeq (${LFA_SUPPORT},1) 596BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 597endif 598 599# This is set to 1 by default when the firmware update 600# support is enabled. Since the BL2 image is not updatable 601ifeq ($(PSA_FWU_SUPPORT),1) 602 SEPARATE_BL2_FIP := 1 603endif 604 605ifeq (${TRANSFER_LIST}, 0) 606ifeq (${SEPARATE_BL2_FIP},1) 607$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 608$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 609else 610$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 611$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 612endif 613endif 614