1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_a510 26 27workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 28 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 29 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ 30 CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH 31workaround_reset_end cortex_a510, ERRATUM(1922240) 32 33check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) 34 35workaround_runtime_start cortex_a510, ERRATUM(2008766), ERRATA_A510_2008766 36 /* Stash ERRSELR_EL1 in x2 */ 37 mrs x2, ERRSELR_EL1 38 39 /* Select error record 0 and clear ED bit */ 40 msr ERRSELR_EL1, xzr 41 sysreg_bit_clear ERXCTLR_EL1, ERXCTLR_ED_BIT 42 43 /* Select error record 1 and clear ED bit */ 44 mov x0, #1 45 msr ERRSELR_EL1, x0 46 sysreg_bit_clear ERXCTLR_EL1, ERXCTLR_ED_BIT 47 48 /* Select error record 2 and clear ED bit */ 49 mov x0, #2 50 msr ERRSELR_EL1, x0 51 sysreg_bit_clear ERXCTLR_EL1, ERXCTLR_ED_BIT 52 53 /* Restore ERRSELR_EL1 from x2 */ 54 msr ERRSELR_EL1, x2 55workaround_runtime_end cortex_a510, ERRATUM(2008766), NO_ISB 56 57check_erratum_ls cortex_a510, ERRATUM(2008766), CPU_REV(1, 3) 58 59workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 60 /* Apply workaround */ 61 mov x0, xzr 62 msr S3_6_C15_C4_0, x0 63 isb 64 65 mov x0, #0x8500000 66 msr S3_6_C15_C4_2, x0 67 68 mov x0, #0x1F700000 69 movk x0, #0x8, lsl #32 70 msr S3_6_C15_C4_3, x0 71 72 mov x0, #0x3F1 73 movk x0, #0x110, lsl #16 74 msr S3_6_C15_C4_1, x0 75workaround_reset_end cortex_a510, ERRATUM(2041909) 76 77check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) 78 79workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 80 /* Apply the workaround by disabling ReadPreferUnique. */ 81 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ 82 CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH 83workaround_reset_end cortex_a510, ERRATUM(2042739) 84 85check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) 86 87workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326 88 /* Apply workaround */ 89 mov x0, #1 90 msr S3_6_C15_C4_0, x0 91 isb 92 93 mov x0, #0x0100 94 movk x0, #0x0E08, lsl #16 95 msr S3_6_C15_C4_2, x0 96 97 mov x0, #0x0300 98 movk x0, #0x0F1F, lsl #16 99 movk x0, #0x0008, lsl #32 100 msr S3_6_C15_C4_3, x0 101 102 mov x0, #0x03F1 103 movk x0, #0x00C0, lsl #16 104 msr S3_6_C15_C4_1, x0 105 106 isb 107workaround_reset_end cortex_a510, ERRATUM(2080326) 108 109check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2) 110 111workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 112 /* 113 * Force L2 allocation of transient lines by setting 114 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. 115 */ 116 mrs x0, CORTEX_A510_CPUECTLR_EL1 117 mov x1, #1 118 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 119 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 120 msr CORTEX_A510_CPUECTLR_EL1, x0 121workaround_reset_end cortex_a510, ERRATUM(2172148) 122 123check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) 124 125workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 126 /* Set bit 18 in CPUACTLR_EL1 */ 127 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 128 CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH 129 130 /* Set bit 25 in CMPXACTLR_EL1 */ 131 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 132 CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH 133 134workaround_reset_end cortex_a510, ERRATUM(2218950) 135 136check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) 137 138workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 139 /* Disable MPMM */ 140 mrs x0, CPUMPMMCR_EL3 141 bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ 142 msr CPUMPMMCR_EL3, x0 143workaround_reset_end cortex_a510, ERRATUM(2250311) 144 145check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) 146 147workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 148 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 149 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ 150 CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH 151workaround_reset_end cortex_a510, ERRATUM(2288014) 152 153check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) 154 155workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941 156 errata_dsu_2313941_wa_impl 157workaround_reset_end cortex_a510, ERRATUM(2313941) 158 159check_erratum_custom_start cortex_a510, ERRATUM(2313941) 160 check_errata_dsu_2313941_impl 161 ret 162check_erratum_custom_end cortex_a510, ERRATUM(2313941) 163 164workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 165 /* 166 * Set CPUACTLR_EL1[17] to 1'b1, which disables 167 * specific microarchitectural clock gating 168 * behaviour. 169 */ 170 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 171workaround_reset_end cortex_a510, ERRATUM(2347730) 172 173check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) 174 175workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 176 /* 177 * Cacheable atomic operations can be forced 178 * to be executed near by setting 179 * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found 180 * in [40:38] of CPUECTLR_EL1. 181 */ 182 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ 183 CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH 184workaround_reset_end cortex_a510, ERRATUM(2371937) 185 186check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) 187 188workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 189 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 190workaround_reset_end cortex_a510, ERRATUM(2666669) 191 192check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) 193 194.global erratum_cortex_a510_2684597_wa 195workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR 196 /* 197 * Many assemblers do not yet understand the "tsb csync" mnemonic, 198 * so use the equivalent hint instruction. 199 */ 200 hint #18 /* tsb csync */ 201workaround_runtime_end cortex_a510, ERRATUM(2684597) 202 203check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) 204 205.global check_erratum_cortex_a510_2971420 206add_erratum_entry cortex_a510, ERRATUM(2971420), ERRATA_A510_2971420 207check_erratum_range cortex_a510, ERRATUM(2971420), CPU_REV(0, 1), CPU_REV(1, 3) 208 209 /* ---------------------------------------------------- 210 * HW will do the cache maintenance while powering down 211 * ---------------------------------------------------- 212 */ 213func cortex_a510_core_pwr_dwn 214 apply_erratum cortex_a510, ERRATUM(2008766), ERRATA_A510_2008766 215 apply_erratum cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, NO_GET_CPU_REV 216 /* --------------------------------------------------- 217 * Enable CPU power down bit in power control register 218 * --------------------------------------------------- 219 */ 220 sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 221 isb 222 ret 223endfunc cortex_a510_core_pwr_dwn 224 225cpu_reset_func_start cortex_a510 226 /* Disable speculative loads */ 227 msr SSBS, xzr 228 /* skip enabling MPMM if this erratum is present */ 229#if ERRATA_A510_2250311 230 /* the cpu_rev_var is kept in x14 */ 231 mov x14, x0 232 bl check_erratum_cortex_a510_2250311 233 cbz x0, skip_mpmm 234#endif 235 enable_mpmm 236skip_mpmm: 237cpu_reset_func_end cortex_a510 238 239 /* --------------------------------------------- 240 * This function provides Cortex-A510 specific 241 * register information for crash reporting. 242 * It needs to return with x6 pointing to 243 * a list of register names in ascii and 244 * x8 - x15 having values of registers to be 245 * reported. 246 * --------------------------------------------- 247 */ 248.section .rodata.cortex_a510_regs, "aS" 249cortex_a510_regs: /* The ascii list of register names to be reported */ 250 .asciz "cpuectlr_el1", "" 251 252func cortex_a510_cpu_reg_dump 253 adr x6, cortex_a510_regs 254 mrs x8, CORTEX_A510_CPUECTLR_EL1 255 ret 256endfunc cortex_a510_cpu_reg_dump 257 258declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 259 cortex_a510_reset_func, \ 260 cortex_a510_core_pwr_dwn 261