| 3cfa3497 | 26-Aug-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
docs(rme): add build and run instructions for FEAT_RME
This patch adds instructions on how to build and run TF-A
with FEAT_RME enabled. The patch also adds code owners for
FEAT_RME.
Signed-off-by:
docs(rme): add build and run instructions for FEAT_RME
This patch adds instructions on how to build and run TF-A
with FEAT_RME enabled. The patch also adds code owners for
FEAT_RME.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Id16dc52cb76b1ea56ac5c3fc38cb0794a62ac2a1
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| 5b18de09 | 11-Jul-2021 |
Zelalem Aweke <zelalem.aweke@arm.com> |
feat(rme): add ENABLE_RME build option and support for RMM image
The changes include:
- A new build option (ENABLE_RME) to enable FEAT_RME
- New image called RMM. RMM is R-EL2 firmware that manage
feat(rme): add ENABLE_RME build option and support for RMM image
The changes include:
- A new build option (ENABLE_RME) to enable FEAT_RME
- New image called RMM. RMM is R-EL2 firmware that manages Realms.
When building TF-A, a path to RMM image can be specified using
the "RMM" build flag. If RMM image is not provided, TRP is built
by default and used as RMM image.
- Support for RMM image in fiptool
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I017c23ef02e465a5198baafd665a60858ecd1b25
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|
| b36fe212 | 29-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to wr
errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to write the value 2'b11 to the PF_MODE bits
in the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: If7dec72578633d37d110d103099e406c3a970ff7
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| 8e140272 | 28-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write
errata: workaround for Neoverse-V1 erratum 2108267
Neoverse-V1 erratum 2108267 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r1p1 of CPU. It is still open. The
workaround is to write the value 2'b11 to the PF_MODE bits in
the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Iedcb84a7ad34af7083116818f49d7296f7d9bf94
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| ef8f0c52 | 28-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
fix(errata): workaround for Neoverse-N2 erratum 2138953
Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'
fix(errata): workaround for Neoverse-N2 erratum 2138953
Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Ife0a4bece7ccf83cc99c1d5f5b5a43084bb69d64
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| 744bdbf7 | 22-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write th
fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
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| cd12b195 | 13-May-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: armv8-R aarch64 fvp_r documentation
Documenting armv8-R aarch64 fvp_r features, boot sequence, and build
procedure.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I
docs: armv8-R aarch64 fvp_r documentation
Documenting armv8-R aarch64 fvp_r features, boot sequence, and build
procedure.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: If75d59acdf0f8a61cea6187967a4c35af2f31c98
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| 5fb061e7 | 27-Jan-2021 |
Gary Morrison <gary.morrison@arm.com> |
chore: fvp_r: Initial No-EL3 and MPU Implementation
For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac39
chore: fvp_r: Initial No-EL3 and MPU Implementation
For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU.
Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I439ac3915b982ad1e61d24365bdd1584b3070425
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| 114785c9 | 29-Sep-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Cortex-A710 erratum 2083908" into integration |
| 5447302f | 29-Sep-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "build(bl2): enable SP pkg loading for S-EL1 SPMC" into integration |
| 46789a7c | 26-Mar-2021 |
Balint Dobszay <balint.dobszay@arm.com> |
build(bl2): enable SP pkg loading for S-EL1 SPMC
Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.
Signed-off-by: Balint Dobszay <balin
build(bl2): enable SP pkg loading for S-EL1 SPMC
Currently the SP package loading mechanism is only enabled when S-EL2
SPMC is selected. Remove this limitation.
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: I5bf5a32248e85a26d0345cacff7d539eed824cfc
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|
| cb4ec47b | 05-Aug-2021 |
johpow01 <john.powell@arm.com> |
feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn
feat(hcx): add build option to enable FEAT_HCX
FEAT_HCX adds the extended hypervisor configuration register (HCRX_EL2)
and access to this register must be explicitly enabled through the
SCR_EL3.HXEn bit. This patch adds a new build flag ENABLE_FEAT_HCX to
allow the register to be accessed from EL2.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ibb36ad90622f1dc857adab4b0d4d7a89456a522b
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|
| ab5964aa | 26-Sep-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls102
Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition
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| 95fe195d | 16-Sep-2021 |
nayanpatel-arm <nayankumar.patel@arm.com> |
errata: workaround for Cortex-A710 erratum 2083908
Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.
S
errata: workaround for Cortex-A710 erratum 2083908
Cortex-A710 erratum 2083908 is a Cat B erratum that applies to
revision r2p0 and is still open. The workaround is to set
CPUACTLR5_EL1[13] to 1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I876d26a7ac6ab0d7c567a9ec9f34fc0f952589d8
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|
| 2245bb8a | 24-Sep-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "refactor(spmd): boot interface and pass core id" into integration |
| 52a1e9ff | 15-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(docs/nxp/layerscape): add ls1028a soc and board support
Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc5
feat(docs/nxp/layerscape): add ls1028a soc and board support
Update nxp-layerscape to add ls1028a SoC and ls1028ardb board
support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I9c7cc586f3718b488a6757994d65f6df69e7e165
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|
| 45fa1895 | 14-Sep-2021 |
Saurabh Gorecha <sgorecha@codeaurora.org> |
docs(maintainers): update qti maintainer
Add lachit and Sreevyshanavi in qti maintainer
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I48d2378551775a3ad63bc7c3a4e2b62b15c4770d |
| 46ee50e0 | 24-May-2021 |
Saurabh Gorecha <sgorecha@codeaurora.org> |
feat(plat/qti/sc7280): support for qti sc7280 plat
new qti platform sc7280 support addition
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f216
feat(plat/qti/sc7280): support for qti sc7280 plat
new qti platform sc7280 support addition
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f21656c1
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|
| b3210f4d | 17-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS E
Merge changes from topic "TrcDbgExt" into integration
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
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|
| be1eba51 | 15-Sep-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "refactor(tc): use internal trusted storage" into integration |
| 38f79045 | 10-Aug-2021 |
Davidson K <davidson.kumaresan@arm.com> |
refactor(tc): use internal trusted storage
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secu
refactor(tc): use internal trusted storage
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secure storage and adding support for the
internal trusted storage.
And enable external SP images in BL2 config for TC, so that
we do not have to modify this file whenever the list of SPs
changes. It is already implemented for fvp in the below commit.
commit 33993a3737737a03ee5a9d386d0a027bdc947c9c
Author: Balint Dobszay <balint.dobszay@arm.com>
Date: Fri Mar 26 15:19:11 2021 +0100
feat(fvp): enable external SP images in BL2 config
Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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|
| e693013b | 15-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(ff-a): fix specification naming" into integration |
| ac61bee5 | 15-Sep-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(ff-a): managed exit parameter separation" into integration |
| 0a948cd2 | 09-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(docs-contributing.rst): fix formatting for code snippet" into integration |
| 9ecf9438 | 09-Sep-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "docs(stm32mp1): update doc for FIP/FCONF" into integration |