errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a

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errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force

errata: workaround for Neoverse N2 erratum 2067956

Neoverse N2 erratum 2067956 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.
This workaround works on revision r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21

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feat(gic600ae): introduce support for Fault Management Unit

The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:

* Provides software the

feat(gic600ae): introduce support for Fault Management Unit

The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:

* Provides software the means to enable or disable a Safety Mechanism
within a GIC block.
* Receives error signaling from all Safety Mechanisms within other GIC
blocks.
* Maintains error records for each GIC block, for software inspection
and provides information on the source of the error.
* Retains error records across functional reset.
* Enables software error recovery testing by providing error injection
capabilities in a Safety Mechanism.

This patch introduces support to enable error detection for all safety
mechanisms provided by the FMU. Platforms are expected to invoke the
initialization function during cold boot.

The support for the FMU is guarded by the GICV3_SUPPORT_GIC600AE_FMU
makefile variable. The default value of this variable is '0'.

Change-Id: I421c3d059624ddefd174cb1140a2d2a2296be0c6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "errata: workaround for Neoverse-N2 errata 2002655" into integration

Merge changes I1e8c2bc3,I9bcff306 into integration

* changes:
errata: workaround for Cortex-A710 errata 2081180
errata: workaround for Cortex-A710 errata 1987031

errata: workaround for Neoverse-N2 errata 2002655

Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.

Neoverse-N2 SDEN: https://d

errata: workaround for Neoverse-N2 errata 2002655

Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of
the Neoverse-N2 processor core, and it is still open.

Neoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1380418146807527abd97cdd4918265949ba5c01

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Merge "docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options" into integration

Merge changes I75a4554a,Idce603e4 into integration

* changes:
feat(plat/marvell): introduce t9130_cex7_eval
feat(plat/marvell/a8k): allow overriding default paths

Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration

feat(trf): enable trace filter control register access from lower NS EL

Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2

feat(trf): enable trace filter control register access from lower NS EL

Introduced a build flag 'ENABLE_TRF_FOR_NS' to enable trace filter
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: If3f53b8173a5573424b9a405a4bd8c206ffdeb8c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(sys_reg_trace): enable trace system registers access from lower NS ELs

Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when N

feat(sys_reg_trace): enable trace system registers access from lower NS ELs

Introduced a build flag 'ENABLE_SYS_REG_TRACE_FOR_NS' to enable trace
system registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: Idc1acede4186e101758cbf7bed5af7b634d7d18d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(trbe): enable access to trace buffer control registers from lower NS EL

Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when N

feat(trbe): enable access to trace buffer control registers from lower NS EL

Introduced a build flag 'ENABLE_TRBE_FOR_NS' to enable trace buffer
control registers access in NS-EL2, or NS-EL1 (when NS-EL2 is
implemented but unused).

Change-Id: I285a672ccd395eebd377714c992bb21062a729cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(plat/marvell): introduce t9130_cex7_eval

This patch adds the necessary files to support
the SolidRun CN913X CEx7 Evaluation Board.

Because the DRAM connectivity and SerDes settings
is shared w

feat(plat/marvell): introduce t9130_cex7_eval

This patch adds the necessary files to support
the SolidRun CN913X CEx7 Evaluation Board.

Because the DRAM connectivity and SerDes settings
is shared with the CN913X DB - reuse relevant
board-specific files.

Change-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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errata: workaround for Cortex-A710 errata 2081180

Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN:

errata: workaround for Cortex-A710 errata 2081180

Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542

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fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default

It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug

fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default

It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug found
in U-Boot and Linux kernel driver pci-aardvark.c (PCIe controller driver
for Armada 37xx SoC) which results in SError interrupt caused by AXI
SLVERR on external access (syndrome 0xbf000002) and immediate kernel
panic.

Now when proper patches are in both U-Boot and Linux kernel projects,
this workaround in TF-A should not have to be enabled by default
anymore as it has unwanted side effects like propagating all external
aborts, including non-fatal/correctable into EL3 and making them as
fatal which cause immediate abort.

Add documentation for HANDLE_EA_EL3_FIRST build option into Marvell
Armada build section.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic92b65bf9923505ab682830afb66c2f6cec70491

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errata: workaround for Cortex-A710 errata 1987031

Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN:

errata: workaround for Cortex-A710 errata 1987031

Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179

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errata: workaround for Cortex-A78 errata 1952683

Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.

A78 SDEN : https://develop

errata: workaround for Cortex-A78 errata 1952683

Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.

A78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0

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docs(ff-a): managed exit parameter separation

As of DEN0077A FF-A v1.1 Beta0 section 5.2, managed exit
support is moved out of messaging-method field and is described in a
separate field.

Signed-of

docs(ff-a): managed exit parameter separation

As of DEN0077A FF-A v1.1 Beta0 section 5.2, managed exit
support is moved out of messaging-method field and is described in a
separate field.

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: Icb12d9dc0d10b11c105dc1920e5212b0359af147

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docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options

Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.

Signed-off-by: Pali Rohár <pali

docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options

Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I852f60569a9a49269ae296c56cc83eb438528bee

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Merge "docs(spmc): threat model document" into integration

feat(cpus): workaround for Cortex A78 AE erratum 1941500

Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting

feat(cpus): workaround for Cortex A78 AE erratum 1941500

Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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docs(spmc): threat model document

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib5f443a6997239d6ba4655d7df6c3fc61d45f991

Merge "feat(cpus): workaround for Cortex A78 AE erratum 1951502" into integration

feat(cpus): workaround for Cortex A78 AE erratum 1951502

Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a

feat(cpus): workaround for Cortex A78 AE erratum 1951502

Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a DMB ST
before acquire atomic instructions without release semantics through a series
of writes to implementation defined system registers.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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refactor(tegra132): deprecate platform

The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support f

refactor(tegra132): deprecate platform

The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support for this legacy platform.

This change removes this platform from the Tegra tree as a result.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a

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