1/* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10#include <neoverse_n2.h> 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22/* -------------------------------------------------- 23 * Errata Workaround for Neoverse N2 Erratum 2002655. 24 * This applies to revision r0p0 of Neoverse N2. it is still open. 25 * Inputs: 26 * x0: variant[4:7] and revision[0:3] of current cpu. 27 * Shall clobber: x0-x17 28 * -------------------------------------------------- 29 */ 30func errata_n2_2002655_wa 31 /* Check revision. */ 32 mov x17, x30 33 bl check_errata_2002655 34 cbz x0, 1f 35 36 /* Apply instruction patching sequence */ 37 ldr x0,=0x6 38 msr S3_6_c15_c8_0,x0 39 ldr x0,=0xF3A08002 40 msr S3_6_c15_c8_2,x0 41 ldr x0,=0xFFF0F7FE 42 msr S3_6_c15_c8_3,x0 43 ldr x0,=0x40000001003ff 44 msr S3_6_c15_c8_1,x0 45 ldr x0,=0x7 46 msr S3_6_c15_c8_0,x0 47 ldr x0,=0xBF200000 48 msr S3_6_c15_c8_2,x0 49 ldr x0,=0xFFEF0000 50 msr S3_6_c15_c8_3,x0 51 ldr x0,=0x40000001003f3 52 msr S3_6_c15_c8_1,x0 53 isb 541: 55 ret x17 56endfunc errata_n2_2002655_wa 57 58func check_errata_2002655 59 /* Applies to r0p0 */ 60 mov x1, #0x00 61 b cpu_rev_var_ls 62endfunc check_errata_2002655 63 64/* --------------------------------------------------------------- 65 * Errata Workaround for Neoverse N2 Erratum 2067956. 66 * This applies to revision r0p0 of Neoverse N2 and is still open. 67 * Inputs: 68 * x0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: x0-x17 70 * --------------------------------------------------------------- 71 */ 72func errata_n2_2067956_wa 73 /* Compare x0 against revision r0p0 */ 74 mov x17, x30 75 bl check_errata_2067956 76 cbz x0, 1f 77 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 78 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 79 msr NEOVERSE_N2_CPUACTLR_EL1, x1 801: 81 ret x17 82endfunc errata_n2_2067956_wa 83 84func check_errata_2067956 85 /* Applies to r0p0 */ 86 mov x1, #0x00 87 b cpu_rev_var_ls 88endfunc check_errata_2067956 89 90/* --------------------------------------------------------------- 91 * Errata Workaround for Neoverse N2 Erratum 2025414. 92 * This applies to revision r0p0 of Neoverse N2 and is still open. 93 * Inputs: 94 * x0: variant[4:7] and revision[0:3] of current cpu. 95 * Shall clobber: x0-x17 96 * --------------------------------------------------------------- 97 */ 98func errata_n2_2025414_wa 99 /* Compare x0 against revision r0p0 */ 100 mov x17, x30 101 bl check_errata_2025414 102 cbz x0, 1f 103 mrs x1, NEOVERSE_N2_CPUECTLR_EL1 104 orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT 105 msr NEOVERSE_N2_CPUECTLR_EL1, x1 106 1071: 108 ret x17 109endfunc errata_n2_2025414_wa 110 111func check_errata_2025414 112 /* Applies to r0p0 */ 113 mov x1, #0x00 114 b cpu_rev_var_ls 115endfunc check_errata_2025414 116 117/* --------------------------------------------------------------- 118 * Errata Workaround for Neoverse N2 Erratum 2189731. 119 * This applies to revision r0p0 of Neoverse N2 and is still open. 120 * Inputs: 121 * x0: variant[4:7] and revision[0:3] of current cpu. 122 * Shall clobber: x0-x17 123 * --------------------------------------------------------------- 124 */ 125func errata_n2_2189731_wa 126 /* Compare x0 against revision r0p0 */ 127 mov x17, x30 128 bl check_errata_2189731 129 cbz x0, 1f 130 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 131 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 132 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 133 1341: 135 ret x17 136endfunc errata_n2_2189731_wa 137 138func check_errata_2189731 139 /* Applies to r0p0 */ 140 mov x1, #0x00 141 b cpu_rev_var_ls 142endfunc check_errata_2189731 143 144/* -------------------------------------------------- 145 * Errata Workaround for Neoverse N2 Erratum 2138956. 146 * This applies to revision r0p0 of Neoverse N2. it is still open. 147 * Inputs: 148 * x0: variant[4:7] and revision[0:3] of current cpu. 149 * Shall clobber: x0-x17 150 * -------------------------------------------------- 151 */ 152func errata_n2_2138956_wa 153 /* Check revision. */ 154 mov x17, x30 155 bl check_errata_2138956 156 cbz x0, 1f 157 158 /* Apply instruction patching sequence */ 159 ldr x0,=0x3 160 msr S3_6_c15_c8_0,x0 161 ldr x0,=0xF3A08002 162 msr S3_6_c15_c8_2,x0 163 ldr x0,=0xFFF0F7FE 164 msr S3_6_c15_c8_3,x0 165 ldr x0,=0x10002001003FF 166 msr S3_6_c15_c8_1,x0 167 ldr x0,=0x4 168 msr S3_6_c15_c8_0,x0 169 ldr x0,=0xBF200000 170 msr S3_6_c15_c8_2,x0 171 ldr x0,=0xFFEF0000 172 msr S3_6_c15_c8_3,x0 173 ldr x0,=0x10002001003F3 174 msr S3_6_c15_c8_1,x0 175 isb 1761: 177 ret x17 178endfunc errata_n2_2138956_wa 179 180func check_errata_2138956 181 /* Applies to r0p0 */ 182 mov x1, #0x00 183 b cpu_rev_var_ls 184endfunc check_errata_2138956 185 186/* -------------------------------------------------- 187 * Errata Workaround for Neoverse N2 Erratum 2242415. 188 * This applies to revision r0p0 of Neoverse N2. it is still open. 189 * Inputs: 190 * x0: variant[4:7] and revision[0:3] of current cpu. 191 * Shall clobber: x0-x1, x17 192 * -------------------------------------------------- 193 */ 194func errata_n2_2242415_wa 195 /* Check revision. */ 196 mov x17, x30 197 bl check_errata_2242415 198 cbz x0, 1f 199 200 /* Apply instruction patching sequence */ 201 mrs x1, NEOVERSE_N2_CPUACTLR_EL1 202 orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 203 msr NEOVERSE_N2_CPUACTLR_EL1, x1 2041: 205 ret x17 206endfunc errata_n2_2242415_wa 207 208func check_errata_2242415 209 /* Applies to r0p0 */ 210 mov x1, #0x00 211 b cpu_rev_var_ls 212endfunc check_errata_2242415 213 214/* -------------------------------------------------- 215 * Errata Workaround for Neoverse N2 Erratum 2138953. 216 * This applies to revision r0p0 of Neoverse N2. it is still open. 217 * Inputs: 218 * x0: variant[4:7] and revision[0:3] of current cpu. 219 * Shall clobber: x0-x1, x17 220 * -------------------------------------------------- 221 */ 222func errata_n2_2138953_wa 223 /* Check revision. */ 224 mov x17, x30 225 bl check_errata_2138953 226 cbz x0, 1f 227 228 /* Apply instruction patching sequence */ 229 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 230 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV 231 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH 232 msr NEOVERSE_N2_CPUECTLR2_EL1, x1 2331: 234 ret x17 235endfunc errata_n2_2138953_wa 236 237func check_errata_2138953 238 /* Applies to r0p0 */ 239 mov x1, #0x00 240 b cpu_rev_var_ls 241endfunc check_errata_2138953 242 243/* -------------------------------------------------- 244 * Errata Workaround for Neoverse N2 Erratum 2138958. 245 * This applies to revision r0p0 of Neoverse N2. it is still open. 246 * Inputs: 247 * x0: variant[4:7] and revision[0:3] of current cpu. 248 * Shall clobber: x0-x1, x17 249 * -------------------------------------------------- 250 */ 251func errata_n2_2138958_wa 252 /* Check revision. */ 253 mov x17, x30 254 bl check_errata_2138958 255 cbz x0, 1f 256 257 /* Apply instruction patching sequence */ 258 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 259 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 260 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 2611: 262 ret x17 263endfunc errata_n2_2138958_wa 264 265func check_errata_2138958 266 /* Applies to r0p0 */ 267 mov x1, #0x00 268 b cpu_rev_var_ls 269endfunc check_errata_2138958 270 271/* -------------------------------------------------- 272 * Errata Workaround for Neoverse N2 Erratum 2242400. 273 * This applies to revision r0p0 of Neoverse N2. it is still open. 274 * Inputs: 275 * x0: variant[4:7] and revision[0:3] of current cpu. 276 * Shall clobber: x0-x1, x17 277 * -------------------------------------------------- 278 */ 279func errata_n2_2242400_wa 280 /* Check revision. */ 281 mov x17, x30 282 bl check_errata_2242400 283 cbz x0, 1f 284 285 /* Apply instruction patching sequence */ 286 mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 287 orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 288 msr NEOVERSE_N2_CPUACTLR5_EL1, x1 289 ldr x0, =0x2 290 msr S3_6_c15_c8_0, x0 291 ldr x0, =0x10F600E000 292 msr S3_6_c15_c8_2, x0 293 ldr x0, =0x10FF80E000 294 msr S3_6_c15_c8_3, x0 295 ldr x0, =0x80000000003FF 296 msr S3_6_c15_c8_1, x0 297 isb 2981: 299 ret x17 300endfunc errata_n2_2242400_wa 301 302func check_errata_2242400 303 /* Applies to r0p0 */ 304 mov x1, #0x00 305 b cpu_rev_var_ls 306endfunc check_errata_2242400 307 308 /* ------------------------------------------- 309 * The CPU Ops reset function for Neoverse N2. 310 * ------------------------------------------- 311 */ 312func neoverse_n2_reset_func 313 mov x19, x30 314 315 /* Check if the PE implements SSBS */ 316 mrs x0, id_aa64pfr1_el1 317 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 318 b.eq 1f 319 320 /* Disable speculative loads */ 321 msr SSBS, xzr 3221: 323 /* Force all cacheable atomic instructions to be near */ 324 mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 325 orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 326 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 327 328#if ERRATA_N2_2067956 329 mov x0, x18 330 bl errata_n2_2067956_wa 331#endif 332 333#if ERRATA_N2_2025414 334 mov x0, x18 335 bl errata_n2_2025414_wa 336#endif 337 338#if ERRATA_N2_2189731 339 mov x0, x18 340 bl errata_n2_2189731_wa 341#endif 342 343 344#if ERRATA_N2_2138956 345 mov x0, x18 346 bl errata_n2_2138956_wa 347#endif 348 349#if ERRATA_N2_2138953 350 mov x0, x18 351 bl errata_n2_2138953_wa 352#endif 353 354#if ERRATA_N2_2242415 355 mov x0, x18 356 bl errata_n2_2242415_wa 357#endif 358 359#if ERRATA_N2_2138958 360 mov x0, x18 361 bl errata_n2_2138958_wa 362#endif 363 364#if ERRATA_N2_2242400 365 mov x0, x18 366 bl errata_n2_2242400_wa 367#endif 368 369#if ENABLE_AMU 370 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 371 mrs x0, cptr_el3 372 orr x0, x0, #TAM_BIT 373 msr cptr_el3, x0 374 375 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 376 mrs x0, cptr_el2 377 orr x0, x0, #TAM_BIT 378 msr cptr_el2, x0 379 380 /* No need to enable the counters as this would be done at el3 exit */ 381#endif 382 383#if NEOVERSE_Nx_EXTERNAL_LLC 384 /* Some systems may have External LLC, core needs to be made aware */ 385 mrs x0, NEOVERSE_N2_CPUECTLR_EL1 386 orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT 387 msr NEOVERSE_N2_CPUECTLR_EL1, x0 388#endif 389 390 bl cpu_get_rev_var 391 mov x18, x0 392 393#if ERRATA_N2_2002655 394 mov x0, x18 395 bl errata_n2_2002655_wa 396#endif 397 398 isb 399 ret x19 400endfunc neoverse_n2_reset_func 401 402func neoverse_n2_core_pwr_dwn 403 /* --------------------------------------------------- 404 * Enable CPU power down bit in power control register 405 * No need to do cache maintenance here. 406 * --------------------------------------------------- 407 */ 408 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 409 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 410 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 411 isb 412 ret 413endfunc neoverse_n2_core_pwr_dwn 414 415#if REPORT_ERRATA 416/* 417 * Errata printing function for Neoverse N2 cores. Must follow AAPCS. 418 */ 419func neoverse_n2_errata_report 420 stp x8, x30, [sp, #-16]! 421 422 bl cpu_get_rev_var 423 mov x8, x0 424 425 /* 426 * Report all errata. The revision-variant information is passed to 427 * checking functions of each errata. 428 */ 429 report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 430 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 431 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 432 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 433 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 434 report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 435 report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 436 report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 437 report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 438 439 ldp x8, x30, [sp], #16 440 ret 441endfunc neoverse_n2_errata_report 442#endif 443 444 /* --------------------------------------------- 445 * This function provides Neoverse N2 specific 446 * register information for crash reporting. 447 * It needs to return with x6 pointing to 448 * a list of register names in ASCII and 449 * x8 - x15 having values of registers to be 450 * reported. 451 * --------------------------------------------- 452 */ 453.section .rodata.neoverse_n2_regs, "aS" 454neoverse_n2_regs: /* The ASCII list of register names to be reported */ 455 .asciz "cpupwrctlr_el1", "" 456 457func neoverse_n2_cpu_reg_dump 458 adr x6, neoverse_n2_regs 459 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 460 ret 461endfunc neoverse_n2_cpu_reg_dump 462 463declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ 464 neoverse_n2_reset_func, \ 465 neoverse_n2_core_pwr_dwn 466