1# 2# Copyright (c) 2016-2021, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33BL2_AT_EL3 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when BL2_AT_EL3 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 67# must be set to 1 if the platform wants to use this feature in the Secure 68# world. It is not needed to use it in the Non-secure world. 69CTX_INCLUDE_PAUTH_REGS := 0 70 71# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 72# This must be set to 1 if architecture implements Nested Virtualization 73# Extension and platform wants to use this feature in the Secure world 74CTX_INCLUDE_NEVE_REGS := 0 75 76# Debug build 77DEBUG := 0 78 79# By default disable authenticated decryption support. 80DECRYPTION_SUPPORT := none 81 82# Build platform 83DEFAULT_PLAT := fvp 84 85# Disable the generation of the binary image (ELF only). 86DISABLE_BIN_GENERATION := 0 87 88# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 89# compatibility. 90DISABLE_MTPMU := 0 91 92# Enable capability to disable authentication dynamically. Only meant for 93# development platforms. 94DYN_DISABLE_AUTH := 0 95 96# Build option to enable MPAM for lower ELs 97ENABLE_MPAM_FOR_LOWER_ELS := 0 98 99# Flag to Enable Position Independant support (PIE) 100ENABLE_PIE := 0 101 102# Flag to enable Performance Measurement Framework 103ENABLE_PMF := 0 104 105# Flag to enable PSCI STATs functionality 106ENABLE_PSCI_STAT := 0 107 108# Flag to enable Realm Management Extension (FEAT_RME) 109ENABLE_RME := 0 110 111# Flag to enable runtime instrumentation using PMF 112ENABLE_RUNTIME_INSTRUMENTATION := 0 113 114# Flag to enable stack corruption protection 115ENABLE_STACK_PROTECTOR := 0 116 117# Flag to enable exception handling in EL3 118EL3_EXCEPTION_HANDLING := 0 119 120# Flag to enable Branch Target Identification. 121# Internal flag not meant for direct setting. 122# Use BRANCH_PROTECTION to enable BTI. 123ENABLE_BTI := 0 124 125# Flag to enable Pointer Authentication. 126# Internal flag not meant for direct setting. 127# Use BRANCH_PROTECTION to enable PAUTH. 128ENABLE_PAUTH := 0 129 130# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 131ENABLE_FEAT_HCX := 0 132 133# By default BL31 encryption disabled 134ENCRYPT_BL31 := 0 135 136# By default BL32 encryption disabled 137ENCRYPT_BL32 := 0 138 139# Default dummy firmware encryption key 140ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 141 142# Default dummy nonce for firmware encryption 143ENC_NONCE := 1234567890abcdef12345678 144 145# Build flag to treat usage of deprecated platform and framework APIs as error. 146ERROR_DEPRECATED := 0 147 148# Fault injection support 149FAULT_INJECTION_SUPPORT := 0 150 151# Byte alignment that each component in FIP is aligned to 152FIP_ALIGN := 0 153 154# Default FIP file name 155FIP_NAME := fip.bin 156 157# Default FWU_FIP file name 158FWU_FIP_NAME := fwu_fip.bin 159 160# By default firmware encryption with SSK 161FW_ENC_STATUS := 0 162 163# For Chain of Trust 164GENERATE_COT := 0 165 166# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 167# default, they are for Secure EL1. 168GICV2_G0_FOR_EL3 := 0 169 170# Route External Aborts to EL3. Disabled by default; External Aborts are handled 171# by lower ELs. 172HANDLE_EA_EL3_FIRST := 0 173 174# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 175# The default value is sha256. 176HASH_ALG := sha256 177 178# Whether system coherency is managed in hardware, without explicit software 179# operations. 180HW_ASSISTED_COHERENCY := 0 181 182# Set the default algorithm for the generation of Trusted Board Boot keys 183KEY_ALG := rsa 184 185# Set the default key size in case KEY_ALG is rsa 186ifeq ($(KEY_ALG),rsa) 187KEY_SIZE := 2048 188endif 189 190# Option to build TF with Measured Boot support 191MEASURED_BOOT := 0 192 193# NS timer register save and restore 194NS_TIMER_SWITCH := 0 195 196# Include lib/libc in the final image 197OVERRIDE_LIBC := 0 198 199# Build PL011 UART driver in minimal generic UART mode 200PL011_GENERIC_UART := 0 201 202# By default, consider that the platform's reset address is not programmable. 203# The platform Makefile is free to override this value. 204PROGRAMMABLE_RESET_ADDRESS := 0 205 206# Flag used to choose the power state format: Extended State-ID or Original 207PSCI_EXTENDED_STATE_ID := 0 208 209# Enable RAS support 210RAS_EXTENSION := 0 211 212# By default, BL1 acts as the reset handler, not BL31 213RESET_TO_BL31 := 0 214 215# For Chain of Trust 216SAVE_KEYS := 0 217 218# Software Delegated Exception support 219SDEI_SUPPORT := 0 220 221# True Random Number firmware Interface 222TRNG_SUPPORT := 0 223 224# SMCCC PCI support 225SMC_PCI_SUPPORT := 0 226 227# Whether code and read-only data should be put on separate memory pages. The 228# platform Makefile is free to override this value. 229SEPARATE_CODE_AND_RODATA := 0 230 231# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 232# separate memory region, which may be discontiguous from the rest of BL31. 233SEPARATE_NOBITS_REGION := 0 234 235# If the BL31 image initialisation code is recalimed after use for the secondary 236# cores stack 237RECLAIM_INIT_CODE := 0 238 239# SPD choice 240SPD := none 241 242# Enable the Management Mode (MM)-based Secure Partition Manager implementation 243SPM_MM := 0 244 245# Use SPM at S-EL2 as a default config for SPMD 246SPMD_SPM_AT_SEL2 := 1 247 248# Flag to introduce an infinite loop in BL1 just before it exits into the next 249# image. This is meant to help debugging the post-BL2 phase. 250SPIN_ON_BL1_EXIT := 0 251 252# Flags to build TF with Trusted Boot support 253TRUSTED_BOARD_BOOT := 0 254 255# Build option to choose whether Trusted Firmware uses Coherent memory or not. 256USE_COHERENT_MEM := 1 257 258# Build option to add debugfs support 259USE_DEBUGFS := 0 260 261# Build option to fconf based io 262ARM_IO_IN_DTB := 0 263 264# Build option to support SDEI through fconf 265SDEI_IN_FCONF := 0 266 267# Build option to support Secure Interrupt descriptors through fconf 268SEC_INT_DESC_IN_FCONF := 0 269 270# Build option to choose whether Trusted Firmware uses library at ROM 271USE_ROMLIB := 0 272 273# Build option to choose whether the xlat tables of BL images can be read-only. 274# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 275# which is the per BL-image option that actually enables the read-only tables 276# API. The reason for having this additional option is to have a common high 277# level makefile where we can check for incompatible features/build options. 278ALLOW_RO_XLAT_TABLES := 0 279 280# Chain of trust. 281COT := tbbr 282 283# Use tbbr_oid.h instead of platform_oid.h 284USE_TBBR_DEFS := 1 285 286# Build verbosity 287V := 0 288 289# Whether to enable D-Cache early during warm boot. This is usually 290# applicable for platforms wherein interconnect programming is not 291# required to enable cache coherency after warm reset (eg: single cluster 292# platforms). 293WARMBOOT_ENABLE_DCACHE_EARLY := 0 294 295# Build option to enable/disable the Statistical Profiling Extensions 296ENABLE_SPE_FOR_LOWER_ELS := 1 297 298# SPE is only supported on AArch64 so disable it on AArch32. 299ifeq (${ARCH},aarch32) 300 override ENABLE_SPE_FOR_LOWER_ELS := 0 301endif 302 303# Include Memory Tagging Extension registers in cpu context. This must be set 304# to 1 if the platform wants to use this feature in the Secure world and MTE is 305# enabled at ELX. 306CTX_INCLUDE_MTE_REGS := 0 307 308ENABLE_AMU := 0 309ENABLE_AMU_AUXILIARY_COUNTERS := 0 310ENABLE_AMU_FCONF := 0 311AMU_RESTRICT_COUNTERS := 0 312 313# By default, enable Scalable Vector Extension if implemented only for Non-secure 314# lower ELs 315# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 316ifneq (${ARCH},aarch32) 317 ENABLE_SVE_FOR_NS := 1 318 ENABLE_SVE_FOR_SWD := 0 319else 320 override ENABLE_SVE_FOR_NS := 0 321 override ENABLE_SVE_FOR_SWD := 0 322endif 323 324SANITIZE_UB := off 325 326# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 327# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 328# Default: disabled 329USE_SPINLOCK_CAS := 0 330 331# Enable Link Time Optimization 332ENABLE_LTO := 0 333 334# Build flag to include EL2 registers in cpu context save and restore during 335# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 336# Default is 0. 337CTX_INCLUDE_EL2_REGS := 0 338 339# Enable Memory tag extension which is supported for architecture greater 340# than Armv8.5-A 341# By default it is set to "no" 342SUPPORT_STACK_MEMTAG := no 343 344# Select workaround for AT speculative behaviour. 345ERRATA_SPECULATIVE_AT := 0 346 347# Trap RAS error record access from lower EL 348RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 349 350# Build option to create cot descriptors using fconf 351COT_DESC_IN_DTB := 0 352 353# Build option to provide openssl directory path 354OPENSSL_DIR := /usr 355 356# Build option to use the SP804 timer instead of the generic one 357USE_SP804_TIMER := 0 358 359# Build option to define number of firmware banks, used in firmware update 360# metadata structure. 361NR_OF_FW_BANKS := 2 362 363# Build option to define number of images in firmware bank, used in firmware 364# update metadata structure. 365NR_OF_IMAGES_IN_FW_BANK := 1 366 367# Disable Firmware update support by default 368PSA_FWU_SUPPORT := 0 369 370# By default, disable access of trace buffer control registers from NS 371# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 372# if FEAT_TRBE is implemented. 373# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 374# AArch32. 375ifneq (${ARCH},aarch32) 376 ENABLE_TRBE_FOR_NS := 0 377else 378 override ENABLE_TRBE_FOR_NS := 0 379endif 380 381# By default, disable access of trace system registers from NS lower 382# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 383# system register trace is implemented. 384ENABLE_SYS_REG_TRACE_FOR_NS := 0 385 386# By default, disable trace filter control registers access to NS 387# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 388# if FEAT_TRF is implemented. 389ENABLE_TRF_FOR_NS := 0 390